( en | de | ru )

 

Disambiguation of "Lin, Mu-Shan"

Author of the publication

copydeleteadd this publication to your clipboard
A 7-nm 4-GHz Arm¹-Core-Based CoWoS¹ Chiplet Design for High-Performance Computing.

, , , , , , , , , , , , , , , , and . IEEE J. Solid State Circuits, 55 (4): 956-966 (2020)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Shan Lin

I-Shan Lin

Shan Tien Lin

Chung-Lin Shan

Shan-Shan Zhan

 

Other publications of authors with the same name

A 1 Tbit/s Bandwidth 1024 b PLL/DLL-Less eDRAM PHY Using 0.3 V 0.105 mW/Gbps Low-Swing IO for CoWoS Application., , , , , , , , , and 5 other author(s). IEEE J. Solid State Circuits, 49 (4): 1063-1074 (2014)A 7-nm 4-GHz Arm¹-Core-Based CoWoS¹ Chiplet Design for High-Performance Computing., , , , , , , , , and 7 other author(s). IEEE J. Solid State Circuits, 55 (4): 956-966 (2020)A 2.5-8Gb/s transceiver with 5-tap DFE and Second order CDR against 28-inch channel and 5000ppm SSC in 40nm CMOS technology., , , , , , , , , and 7 other author(s). CICC, page 1-4. IEEE, (2010)A 7nm 4GHz Arm®-core-based CoWoS® Chiplet Design for High Performance Computing., , , , , , , , , and 7 other author(s). VLSI Circuits, page 28-. IEEE, (2019)A 16nm 256-bit wide 89.6GByte/s total bandwidth in-package interconnect with 0.3V swing and 0.062pJ/bit power in InFO package., , , , , , , , , and 4 other author(s). Hot Chips Symposium, page 1-32. IEEE, (2016)Interconnect in the Era of 3DIC., , , and . CICC, page 1-5. IEEE, (2022)Personalized Optimal Search in Local Query Expansion., and . ROCLING, Association for Computational Linguistics and Chinese Language Processing (ACLCLP), Taiwan, (2006)