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Disambiguation of "Tsai, Chien-Chun"

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A 7-nm 4-GHz Arm¹-Core-Based CoWoS¹ Chiplet Design for High-Performance Computing.

, , , , , , , , , , , , , , , , and . IEEE J. Solid State Circuits, 55 (4): 956-966 (2020)

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Schi-chien Tsai

Yu-Chun Tsai

Yin-chun Tsai-Stürenberg

Chieh Chien

Rey-Djin Chien

 

Other publications of authors with the same name

Impact of guard ring layout on the stacked low-voltage PMOS for high-voltage ESD protection., , , , , , , , and . ECCTD, page 1-4. IEEE, (2015)A 7nm 4GHz Arm®-core-based CoWoS® Chiplet Design for High Performance Computing., , , , , , , , , and 7 other author(s). VLSI Circuits, page 28-. IEEE, (2019)A 16nm 256-bit wide 89.6GByte/s total bandwidth in-package interconnect with 0.3V swing and 0.062pJ/bit power in InFO package., , , , , , , , , and 4 other author(s). Hot Chips Symposium, page 1-32. IEEE, (2016)The Implementation of an HSM-Based Smart Meter for Supporting DLMS/COSEM Security Suite 1., , , and . IoTBDS, page 123-130. SCITEPRESS, (2023)Interconnect in the Era of 3DIC., , , and . CICC, page 1-5. IEEE, (2022)A 2.5-8Gb/s transceiver with 5-tap DFE and Second order CDR against 28-inch channel and 5000ppm SSC in 40nm CMOS technology., , , , , , , , , and 7 other author(s). CICC, page 1-4. IEEE, (2010)Implementing OIML R46 Communication Unit for DLMS/COSEM Security Suite 1 and Passing CTT V3.1 Test., , , and . ICNSC, page 1-6. IEEE, (2023)Energy Efficient Design Through Design and Technology Co-Optimization Near the Finish Line of CMOS Scaling., , , , and . A-SSCC, page 1-3. IEEE, (2021)An Interpolated Flying-Adder-Based Frequency Synthesizer., and . J. Electr. Comput. Eng., (2011)A 7-nm 4-GHz Arm¹-Core-Based CoWoS¹ Chiplet Design for High-Performance Computing., , , , , , , , , and 7 other author(s). IEEE J. Solid State Circuits, 55 (4): 956-966 (2020)