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Disambiguation of "Tam, King-Ho"

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A 7-nm 4-GHz Arm¹-Core-Based CoWoS¹ Chiplet Design for High-Performance Computing.

, , , , , , , , , , , , , , , , and . IEEE J. Solid State Circuits, 55 (4): 956-966 (2020)

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Lê Tâm

Tam Nguyen

Tâm Huynh

Jason Tam

Tam Bülow

 

Other publications of authors with the same name

Challenges in gate level modeling for delay and SI at 65nm and below., , and . DAC, page 468-473. ACM, (2008)Criticality-dependency-aware timing characterization and analysis., , and . DAC, page 167:1-167:6. ACM, (2015)Simultaneous buffer insertion and wire sizing considering systematic CMP variation and random leff variation., , , and . ISPD, page 78-85. ACM, (2005)A 7-nm 4-GHz Arm¹-Core-Based CoWoS¹ Chiplet Design for High-Performance Computing., , , , , , , , , and 7 other author(s). IEEE J. Solid State Circuits, 55 (4): 956-966 (2020)Fast dual-vdd buffering based on interconnect prediction and sampling., , , and . SLIP, page 95-102. ACM, (2007)A 7nm 4GHz Arm®-core-based CoWoS® Chiplet Design for High Performance Computing., , , , , , , , , and 7 other author(s). VLSI Circuits, page 28-. IEEE, (2019)Power optimal dual-Vdd buffered tree considering buffer stations and blockages., and . DAC, page 497-502. ACM, (2005)Power-optimal repeater insertion considering Vdd and Vth as design freedoms., , and . ISLPED, page 137-142. ACM, (2005)Design and manufacturing process co-optimization in nano-technology., , , , , and . ICCAD, page 574-581. IEEE, (2014)Leveraging Delay Slack in Flip-Flop and Buffer Insertion for Power Reduction., , , , and . ISQED, page 69-74. IEEE Computer Society, (2004)