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Disambiguation of "Bhatia, Dinesh"

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Tabu Search: Ultra-Fast Placement for FPGAs.

, and . FPL, volume 1673 of Lecture Notes in Computer Science, page 81-90. Springer, (1999)

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To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Dinesh Lathia

Dinesh Adhikary

Dinesh Thilakarathna

Aman Bhatia

Sanil Bhatia

 

Other publications of authors with the same name

A smart door access system using finger print biometric system., and . IJMEI, 6 (3): 274-280 (2014)Generalized segmented channel routing., and . Great Lakes Symposium on VLSI, page 64-69. IEEE, (1994)A priori wirelength and interconnect estimation based on circuit characteristic., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 24 (7): 1054-1065 (2005)Improved Algorithms for Routing on Two-Dimensional Grids., , , and . WG, volume 657 of Lecture Notes in Computer Science, page 114-122. Springer, (1992)fGREP - Fast Generic Routing Demand Estimation for Placed FPGA Circuits., , and . FPL, volume 2147 of Lecture Notes in Computer Science, page 37-47. Springer, (2001)Machine learning based fast and accurate High Level Synthesis design space exploration: From graph to synthesis., , and . Integr., (2023)Resource requirements and layouts for field programmable interconnection chips., and . IEEE Trans. Very Large Scale Integr. Syst., 8 (3): 346-355 (2000)Resource requirements for field programmable interconnection chips., and . VLSI Design, page 376-380. IEEE Computer Society, (1995)Tabu Search: Ultra-Fast Placement for FPGAs., and . FPL, volume 1673 of Lecture Notes in Computer Science, page 81-90. Springer, (1999)Timing Aware Interconnect Prediction Models for FPGAs., and . FPL, page 167-172. IEEE, (2005)