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Applying TMR in Hardware Accelerators Generated by High-Level Synthesis Design Flow for Mitigating Multiple Bit Upsets in SRAM-Based FPGAs., , , , and . ARC, volume 10216 of Lecture Notes in Computer Science, page 202-213. (2017)Improving approximate-TMR using multi-objective optimization genetic algorithm., , , , , , and . LATS, page 1-6. IEEE, (2018)Applying lockstep in dual-core ARM Cortex-A9 to mitigate radiation-induced soft errors., , and . LASCAS, page 1-4. IEEE, (2017)Comparative Analysis of Inference Errors in a Neural Network Implemented in SRAM-Based FPGA Induced by Neutron Irradiation and Fault Injection Methods., , , , and . SBCCI, page 1-6. IEEE, (2018)Combining fault tolerance and serialization effort to improve yield in 3D Networks-on-Chip., , , , , , , , and . ICECS, page 125-128. IEEE, (2013)Exploring the inherent fault tolerance of successive approximation algorithms under laser fault injection., , , and . LATS, page 1-6. IEEE, (2018)On the Optimal Design of Triple Modular Redundancy Logic for SRAM-based FPGAs, , , and . CoRR, (2007)Failure Mechanism and Sampling Frequency Dependency on TID Response of SAR ADCs., , , , , , , , , and 1 other author(s). J. Electron. Test., 37 (3): 329-343 (2021)Application-Based Analysis of Register File Criticality for Reliability Assessment in Embedded Microprocessors., , , , and . J. Electron. Test., 31 (2): 139-150 (2015)Exploring the Limitations of Software-based Techniques in SEE Fault Coverage., , , and . J. Electron. Test., 27 (4): 541-550 (2011)