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Fast and Efficient Constraint Evaluation of Analog Layout Using Machine Learning Models., , , , , , , , , and . ASP-DAC, page 158-163. ACM, (2021)Assessing Economic Viability: A Comparative Analysis of Total Cost of Ownership for Domain-Adapted Large Language Models versus State-of-the-art Counterparts in Chip Design Coding Assistance., , , , , and . CoRR, (2024)The ALIGN Open-Source Analog Layout Generator: v1.0 and Beyond (Invited talk)., , , , , , , , , and 3 other author(s). ICCAD, page 54:1-54:2. IEEE, (2020)ALIGN: Open-Source Analog Layout Automation from the Ground Up., , , , , , , , and . DAC, page 77. ACM, (2019)GNNIE: GNN Inference Engine with Load-balancing and Graph-Specific Caching., , , and . CoRR, (2021)A general approach for identifying hierarchical symmetry constraints for analog circuit layout., , , , , and . ICCAD, page 120:1-120:8. IEEE, (2020)Learning from Experience: Applying ML to Analog Circuit Design., , , , , , , , , and 2 other author(s). ISPD, page 55. ACM, (2020)GNN-Based Hierarchical Annotation for Analog Circuits., , , , , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 42 (9): 2801-2814 (September 2023)A Unified Engine for Accelerating GNN Weighting/Aggregation Operations, With Efficient Load Balancing and Graph-Specific Caching., , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 42 (12): 4844-4857 (December 2023)BeGAN: Power Grid Benchmark Generation Using a Process-portable GAN-based Methodology., , , and . ICCAD, page 1-8. IEEE, (2021)