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23.2 A 5Gb/s/pin 8Gb LPDDR4X SDRAM with power-isolated LVSTL and split-die architecture with 2-die ZQ calibration scheme., , , , , , , , , и 27 other автор(ы). ISSCC, стр. 390-391. IEEE, (2017)Design of non-contact 2Gb/s I/O test methods for high bandwidth memory (HBM)., , , , , , , , , и 9 other автор(ы). A-SSCC, стр. 169-172. IEEE, (2016)Defect Analysis and Cost-Effective Resilience Architecture for Future DRAM Devices., , , , , , , , , и 2 other автор(ы). HPCA, стр. 61-72. IEEE Computer Society, (2017)The classification methodology of chip quality using canonical correlation analysis-based variable selection on chip level data., , , , , и . IEEM, стр. 381-385. IEEE, (2015)18.2 A 1.2V 20nm 307GB/s HBM DRAM with at-speed wafer-level I/O test scheme and adaptive refresh considering temperature distribution., , , , , , , , , и 11 other автор(ы). ISSCC, стр. 316-317. IEEE, (2016)A 6.4Gb/s/pin at sub-1V supply voltage TX-interleaving technique for mobile DRAM interface., , , , , , , , , и 6 other автор(ы). VLSIC, стр. 182-. IEEE, (2015)Novel Deep Trench Buried-Body-Contact (DBBC) of 4F2 cell for sub 30nm DRAM technology., , , , , , , , , и 2 other автор(ы). ESSDERC, стр. 193-196. IEEE, (2012)A 31 ns Random Cycle VCAT-Based 4F 2 DRAM With Manufacturability and Enhanced Cell Efficiency., , , , , , , , , и 11 other автор(ы). IEEE J. Solid State Circuits, 45 (4): 880-888 (2010)23.4 An extremely low-standby-power 3.733Gb/s/pin 2Gb LPDDR4 SDRAM for wearable devices., , , , , , , , , и 26 other автор(ы). ISSCC, стр. 394-395. IEEE, (2017)18.1 A 20nm 9Gb/s/pin 8Gb GDDR5 DRAM with an NBTI monitor, jitter reduction techniques and improved power distribution., , , , , , , , , и 7 other автор(ы). ISSCC, стр. 314-315. IEEE, (2016)