Author of the publication

pin 2Gb LPDDR4 SDRAM for wearable devices.

H. Kwon, E. Seo, C. Lee, Y. Seo, G. Han, H. Kim, J. Lee, M. Jang, S. Do, S. Cho, J. Park, S. Doo, J. Shin, S. Jung, H. Kim, I. Im, B. Cho, J. Lee, J. Lee, K. Yu, H. Kim, C. Jeon, H. Park, S. Kim, S. Lee, J. Park, S. Lee, B. Lim, J. Park, Y. Park, H. Kwon, S. Bae, J. Choi, K. Park, S. Jang, and G. Jin. ISSCC, page 394-395. IEEE, (2017)

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Sung-Hwan Choi

Hwan-Ok Jung

Jung-Hwan Kim

Seung Hwan Jung

Jung-Hwan Oh

Other publications of authors with the same name

Design of non-contact 2Gb/s I/O test methods for high bandwidth memory (HBM).H. Lee, S. Kang, H. Yu, W. Yun, J. Jung, S. Ahn, W. Kim, B. Kil, Y. Sung, S. Shin and 9 other author(s). A-SSCC, page 169-172. IEEE, (2016)23.2 A 5Gb/s/pin 8Gb LPDDR4X SDRAM with power-isolated LVSTL and split-die architecture with 2-die ZQ calibration scheme.C. Lee, Y. Eom, J. Park, J. Lee, H. Kim, K. Kim, Y. Choi, H. Chang, J. Kim, J. Bang and 27 other author(s). ISSCC, page 390-391. IEEE, (2017)Design technologies for a 1.2V 2.4Gb/s/pin high capacity DDR4 SDRAM with TSVs.R. Oh, B. Lee, S. Shin, W. Bae, H. Choi, I. Song, Y. Lee, J. Choi, C. Kim, S. Jang and 1 other author(s). VLSIC, page 1-2. IEEE, (2014)A 16Gb LPDDR4X SDRAM with an NBTI-tolerant circuit solution, an SWD PMOS GIDL reduction technique, an adaptive gear-down scheme and a metastable-free DQS aligner in a 10nm class DRAM process.K. Chun, Y. Chu, J. Heo, T. Kim, S. Kim, H. Yang, M. Kim, C. Lee, J. Kim, H. Yoon and 37 other author(s). ISSCC, page 206-208. IEEE, (2018)Dynamic Bit-Width Adaptation in DCT: An Approach to Trade Off Image Quality and Computation Energy.J. Park, J. Choi, and K. Roy. IEEE Trans. Very Large Scale Integr. Syst., 18 (5): 787-793 (2010)O2C: occasional two-cycle operations for dynamic thermal management in high performance in-order microprocessors.S. Ghosh, J. Choi, P. Ndai, and K. Roy. ISLPED, page 189-192. ACM, (2008)Dual-Loop Two-Step ZQ Calibration for Dynamic Voltage-Frequency Scaling in LPDDR4 SDRAM.C. Lee, J. Lee, K. Kim, J. Heo, J. Baek, G. Cha, D. Moon, D. Lee, J. Park, S. Lee and 13 other author(s). IEEE J. Solid State Circuits, 53 (10): 2906-2916 (2018)A 1.2 V 20 nm 307 GB/s HBM DRAM With At-Speed Wafer-Level IO Test Scheme and Adaptive Refresh Considering Temperature Distribution.K. Sohn, W. Yun, R. Oh, C. Oh, S. Seo, M. Park, D. Shin, W. Jung, S. Shin, J. Ryu and 9 other author(s). IEEE J. Solid State Circuits, 52 (1): 250-260 (2017)A 40 mV-Differential-Channel-Swing Transceiver Using a RX Current-Integrating TIA and a TX Pre-Emphasis Equalizer With a CML Driver at 9 Gb/s.I. Yi, S. Lee, S. Bae, Y. Sohn, J. Choi, S. Jang, B. Kim, J. Sim, and H. Park. IEEE Trans. Circuits Syst. I Regul. Pap., 63-I (1): 122-133 (2016)A 4ns Settling Time FVF-Based Fast LDO Using Bandwidth Extension Techniques for HBM3.J. Jung, J. Choi, K. Roh, J. Park, W. Lim, T. Kim, H. Jeong, M. Kwak, J. Youn, J. Ihm and 4 other author(s). A-SSCC, page 1-3. IEEE, (2023)

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Disambiguation of "Choi, Jung-Hwan"

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23.4 An extremely low-standby-power 3.733Gb/s/pin 2Gb LPDDR4 SDRAM for wearable devices.

Please choose a person to relate this publication to

Sung-Hwan Choi

Hwan-Ok Jung

Jung-Hwan Kim

Seung Hwan Jung

Jung-Hwan Oh

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Choi, Jung-Hwan"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML 23.4 An extremely low-standby-power 3.733Gb/s/pin 2Gb LPDDR4 SDRAM for wearable devices.

Please choose a person to relate this publication to

Sung-Hwan Choi

Hwan-Ok Jung

Jung-Hwan Kim

Seung Hwan Jung

Jung-Hwan Oh

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
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23.4 An extremely low-standby-power 3.733Gb/s/pin 2Gb LPDDR4 SDRAM for wearable devices.