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Disambiguation of "Jang, Seong-Jin"

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23.4 An extremely low-standby-power 3.733Gb/s/pin 2Gb LPDDR4 SDRAM for wearable devices.

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Seong-Jin Choi

Kuk Jin Jang

Seong Jin Choi

Ki-Chang Seong

Seunghyeon Seong

 

Other publications of authors with the same name

18.1 A 20nm 9Gb/s/pin 8Gb GDDR5 DRAM with an NBTI monitor, jitter reduction techniques and improved power distribution., , , , , , , , , and 7 other author(s). ISSCC, page 314-315. IEEE, (2016)A Study on Knocking Analysis Simulator Based on CRDI Engine ECU., , and . FGIT-GDC/IESH/CGAG, volume 351 of Communications in Computer and Information Science, page 255-262. Springer, (2012)A sub-0.85V, 6.4GBP/S/Pin TX-Interleaved Transceiver with Fast Wake-Up Time Using 2-Step Charging Control and VOHCalibration in 20NM DRAM Process., , , , , , , , , and 16 other author(s). VLSI Circuits, page 147-148. IEEE, (2018)An Enhanced Built-off-Test Transceiver with Wide-range, Self-calibration Engine for 3.2 Gb/s/pin DDR4 SDRAM., , , , , , , , , and 7 other author(s). A-SSCC, page 139-142. IEEE, (2018)A 16-Gb, 18-Gb/s/pin GDDR6 DRAM With Per-Bit Trainable Single-Ended DFE and PLL-Less Clocking., , , , , , , , , and 29 other author(s). IEEE J. Solid State Circuits, 54 (1): 197-209 (2019)A 60nm 6Gb/s/pin GDDR5 Graphics DRAM with Multifaceted Clocking and ISI/SSN-Reduction Techniques., , , , , , , , , and 16 other author(s). ISSCC, page 278-279. IEEE, (2008)An 80nm 4Gb/s/pin 32b 512Mb GDDR4 Graphics DRAM with Low-Power and Low-Noise Data-Bus Inversion., , , , , , , , , and 19 other author(s). ISSCC, page 492-617. IEEE, (2007)23.7 A time-based receiver with 2-tap DFE for a 12Gb/s/pin single-ended transceiver of mobile DRAM interface in 0.8V 65nm CMOS., , , , , , , , and . ISSCC, page 400-401. IEEE, (2017)A Study on Dynamic Gateway System for MOST GATEWAY Scheduling Algorithm in MOST25 and MOST150 Networks., and . ICHIT (1), volume 6935 of Lecture Notes in Computer Science, page 45-53. Springer, (2011)A 3.2 Gbps/pin 8 Gbit 1.0 V LPDDR4 SDRAM With Integrated ECC Engine for Sub-1 V DRAM Core Operation., , , , , , , , , and 10 other author(s). IEEE J. Solid State Circuits, 50 (1): 178-190 (2015)