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Analysis of the effect of cell parameters on the maximum RRAM array size considering both read and write., , , , and . ESSDERC, page 282-285. IEEE, (2012)High-k Dielectrics and Metal Gates for Future Generation Memory Devices, , , , , , , , , and 28 other author(s). ECS Transactions, 19 (1): 29--40 (2009)A High Throughput Generative Vector Autoregression Model for Stochastic Synapses., , , , , , and . CoRR, (2022)MNEMOSENE: Tile Architecture and Simulator for Memristor-based Computation-in-memory., , , , , , , , and . ACM J. Emerg. Technol. Comput. Syst., 18 (3): 44:1-44:24 (2022)Work-in-Progress: A Universal Instrumentation Platform for Non-Volatile Memories., , , , , , , , , and . CODES+ISSS, page 44-45. IEEE, (2023)System model of neuromorphic sequence learning on a memristive crossbar array., , , , , and . Neuromorph. Comput. Eng., 3 (2): 24002 (June 2023)Reliability aspects of binary vector-matrix-multiplications using ReRAM devices., , , , , , , , , and . Neuromorph. Comput. Eng., 2 (3): 34001 (2022)Sequence learning, prediction, and replay in networks of spiking neurons., , , and . PLoS Comput. Biol., (2022)Bit slicing approaches for variability aware ReRAM CIM macros., , , , and . it Inf. Technol., 65 (1-2): 3-12 (May 2023)Eliminating Capacitive Sneak Paths in Associative Capacitive Networks based on Complementary Resistive Switches for In-Memory Computing., , , , , and . IMW, page 1-4. IEEE, (2023)