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Memristive Device Modeling and Circuit Design Exploration for Computation-in-Memory., , , and . ISCAS, page 1-5. IEEE, (2019)Controllability of multi-level states in memristive device models using a transistor as current compliance during SET operation., , , and . IJCNN, page 1-8. IEEE, (2015)A Complementary Resistive Switch-Based Crossbar Array Adder., , , and . IEEE J. Emerg. Sel. Topics Circuits Syst., 5 (1): 64-74 (2015)Memory Devices: Energy-Space-Time Tradeoffs., , , , , , , and . Proc. IEEE, 98 (12): 2185-2200 (2010)The influence of interfacial (sub)oxide layers on the properties of pristine resistive switching devices., , , , , and . NVMTS, page 1-4. IEEE, (2018)Kogge-Stone Adder Realization using 1S1R Resistive Switching Crossbar Arrays., , , , and . ACM J. Emerg. Technol. Comput. Syst., 14 (2): 30:1-30:14 (2018)Applicability of Well-Established Memristive Models for Simulations of Resistive Switching Devices., , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 61-I (8): 2402-2410 (2014)NEUROTEC I: Neuro-inspired Artificial Intelligence Technologies for the Electronics of the Future., , , , , , , , , and 23 other author(s). DATE, page 957-962. IEEE, (2022)NeuroHammer: Inducing Bit-Flips in Memristive Crossbar Memories., , , , , , , , and . DATE, page 1181-1184. IEEE, (2022)Integration of Physics-Derived Memristor Models with Machine Learning Frameworks., , , and . IEEECONF, page 1142-1146. IEEE, (2022)