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Disambiguation of "Hariyama, Masanori"

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Efficient data transfer scheme using word-pair-encoding-based compression for large-scale text-data processing.

, , , and . APCCAS, page 639-642. IEEE, (2014)

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Hardware-oriented succinct-data-structure based on block-size-constrained compression., , and . SoCPaR, page 136-140. IEEE, (2015)Implementation of an FPGA-Oriented Complex Number Computation Library Using Intel OneAPI DPC++., , and . MWSCAS, page 1-4. IEEE, (2022)Non-Volatile Multi-Context FPGAs Using Hybrid Multiple-Valued/Binary Context Switching Signals., , , and . ERSA, page 309-310. CSREA Press, (2008)Benchmarks for FPGA-Targeted High-Level-Synthesis., , and . CANDAR, page 232-238. IEEE, (2019)Switch Block Architecture for Multi-Context FPGAs Using Hybrid Multiple-Valued/Binary Context Switching Signals., , and . ISMVL, page 17. IEEE Computer Society, (2006)Low-Power Field-Programmable VLSI Processor Using Dynamic Circuits., , and . ISVLSI, page 243-248. IEEE Computer Society, (2004)Design of a Collision Detection VLSI Processor Based on Minimization of Area-Time Products., and . ICRA, page 3691-3696. IEEE Computer Society, (1998)Dual-rail/single-rail hybrid logic design for high-performance asynchronous circuit., , , and . ISCAS, page 3017-3020. IEEE, (2012)Data-Transfer-Bottleneck-Less Architecture for FPGA-Based Quantum Annealing Simulation., , and . CANDAR, page 164-170. IEEE, (2019)Optimal Periodical Memory Allocation for Logic-in-Memory Image Processors., , and . ISVLSI, page 193-198. IEEE Computer Society, (2006)