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Disambiguation of "Okumura, Shunsuke"

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Multiple-Bit-Upset and Single-Bit-Upset Resilient 8T SRAM Bitcell Layout with Divided Wordline Structure.

, , , , and . IEICE Trans. Electron., 95-C (10): 1675-1681 (2012)

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Shunsuke Saito

 

Other publications of authors with the same name

Bit error rate estimation in SRAM considering temperature fluctuation., , , , , , , and . ISQED, page 516-519. IEEE, (2012)0.5-V operation variation-aware word-enhancing cache architecture using 7T/14T hybrid SRAM., , , and . ISLPED, page 219-224. ACM, (2010)A 40-nm 256-Kb Half-Select Resilient 8T SRAM with Sequential Writing Technique., , , , , , and . IEICE Electron. Express, 9 (12): 1023-1029 (2012)A 40-nm 0.5-V 12.9-pJ/Access 8T SRAM Using Low-Energy Disturb Mitigation Scheme., , , , , , and . IEICE Trans. Electron., 95-C (4): 572-578 (2012)A Dependable SRAM with 7T/14T Memory Cells., , , , , and . IEICE Trans. Electron., 92-C (4): 423-432 (2009)A 40-nm Resilient Cache Memory for Dynamic Variation Tolerance Delivering ×91 Failure Rate Improvement under 35% Supply Voltage Fluctuation., , , , , , , , , and 4 other author(s). IEICE Trans. Electron., 97-C (4): 332-341 (2014)Design Choice in 45-nm Dual-Port SRAM - 8T, 10T Single End, and 10T Differential., , , , , , and . IPSJ Trans. Syst. LSI Des. Methodol., (2011)7T SRAM enabling low-energy simultaneous block copy., , , , , and . CICC, page 1-4. IEEE, (2010)Model-based fault injection for failure effect analysis - Evaluation of dependable SRAM for vehicle control units., , , , , , , and . DSN Workshops, page 91-96. IEEE Computer Society, (2011)A 40-nm 256-Kb 0.6-V operation half-select resilient 8T SRAM with sequential writing technique enabling 367-mV VDDmin reduction., , , , , , and . ISQED, page 489-492. IEEE, (2012)