Author of the publication

A new family of semidynamic and dynamic flip-flops with embedded logic for high-performance processors.

, , , , , , , , and . IEEE J. Solid State Circuits, 34 (5): 712-716 (1999)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

Clock-Delayed Domino for Adder and Combinational Logic Desig., and . ICCD, page 332-337. IEEE Computer Society, (1996)Clock-delayed domino for dynamic circuit design., and . IEEE Trans. Very Large Scale Integr. Syst., 8 (4): 425-430 (2000)Domino logic synthesis using complex static gates., , and . ICCAD, page 242-247. ACM / IEEE Computer Society, (1998)A third-generation SPARC V9 64-b microprocessor., , , , , , , , , and 21 other author(s). IEEE J. Solid State Circuits, 35 (11): 1526-1538 (2000)An Automated Shielding Algorithm and Tool For Dynamic Circuits., , , , and . ISQED, page 369-374. IEEE Computer Society, (2000)Output Prediction Logic: A High-Performance CMOS Design Technique., , , , and . ICCD, page 247-254. IEEE Computer Society, (2000)Design and Synthesis of Monotonic Circuits., , and . ICCD, page 569-572. IEEE Computer Society, (1999)Locally clocked pipelines and dynamic logic., , and . IEEE Trans. Very Large Scale Integr. Syst., 10 (1): 58-62 (2002)A new family of semidynamic and dynamic flip-flops with embedded logic for high-performance processors., , , , , , , , and . IEEE J. Solid State Circuits, 34 (5): 712-716 (1999)Delay Minimization and Technology Mapping of Two-Level Structures and Implementation Using Clock-Delayed Domino Logic., , and . DATE, page 277-282. IEEE Computer Society / ACM, (2000)