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Towards high density 3D interconnections., , , , , and . 3DIC, page 1-2. IEEE, (2016)IntAct: A 96-Core Processor With Six Chiplets 3D-Stacked on an Active Interposer With Distributed Interconnects and Integrated Power Management., , , , , , , , , and 18 other author(s). IEEE J. Solid State Circuits, 56 (1): 79-97 (2021)3D integration demonstration of a wireless product with design partitioning., , , , , , , , , and 17 other author(s). 3DIC, page 1-5. IEEE, (2011)2.3 A 220GOPS 96-Core Processor with 6 Chiplets 3D-Stacked on an Active Interposer Offering 0.6ns/mm Latency, 3Tb/s/mm2 Inter-Chiplet Interconnects and 156mW/mm2@ 82%-Peak-Efficiency DC-DC Converters., , , , , , , , , and 18 other author(s). ISSCC, page 46-48. IEEE, (2020)Towards a Complete Direct Hybrid Bonding D2W Integration Flow: Known-Good-Dies and Die Planarization Modules Development., , , , , , , , , and 7 other author(s). 3DIC, page 1-5. IEEE, (2019)Advanced 3D Technologies and Architectures for 3D Smart Image Sensors., , , , , , , , , and 7 other author(s). DATE, page 674-679. IEEE, (2019)Silicon based dry-films evaluation for 2.5D and 3D Wafer-Level system integration improvement., , , , , , , , , and 3 other author(s). 3DIC, page TS1.4.1-TS1.4.8. IEEE, (2015)Experimental Insights Into Thermal Dissipation in TSV-Based 3-D Integrated Circuits., , , , , , , , , and 6 other author(s). IEEE Des. Test, 33 (3): 21-36 (2016)Heat spreading packaging solutions for hybrid bonded 3D-ICs., , , , , , , , , and 2 other author(s). 3DIC, page 1-6. IEEE, (2016)Which interconnects for which 3D applications? Status and perspectives., , , , , and . 3DIC, page 1-6. IEEE, (2013)