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Low-power SRAMs power mode control logic: Failure analysis and test solutions.

, , , , , , and . ITC, page 1-10. IEEE Computer Society, (2012)

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On the reuse of read and write assist circuits to improve test efficiency in low-power SRAMs., , , , , , and . ITC, page 1-10. IEEE Computer Society, (2013)On the Use of Assist Circuits for Improved Coupling Fault Detection in SRAMs., , and . ATS, page 61-66. IEEE Computer Society, (2015)On the Test and Mitigation of Malfunctions in Low-Power SRAMs., , , , , and . J. Electron. Test., 30 (5): 611-627 (2014)An effective BIST architecture for power-gating mechanisms in low-power SRAMs., , , , and . ISQED, page 185-191. IEEE, (2016)Test solution for data retention faults in low-power SRAMs., , , , , , and . DATE, page 442-447. EDA Consortium San Jose, CA, USA / ACM DL, (2013)Low-power SRAMs power mode control logic: Failure analysis and test solutions., , , , , , and . ITC, page 1-10. IEEE Computer Society, (2012)Failure Analysis and Test Solutions for Low-Power SRAMs., , , , , , , and . Asian Test Symposium, page 459-460. IEEE Computer Society, (2011)Defect analysis in power mode control logic of low-power SRAMs., , , , , , and . ETS, page 1. IEEE Computer Society, (2012)Failure mechanisms and test methods for the SRAM TVC write-assist technique., , , and . ETS, page 1-2. IEEE, (2016)A built-in scheme for testing and repairing voltage regulators of low-power srams., , , , , , and . VTS, page 1-6. IEEE Computer Society, (2013)