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Disambiguation of "Fujita, Shinobu"

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Detachable nano-carbon chip with ultra low power.

, , , , , and . DAC, page 631-632. ACM, (2010)

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Toko Fujita

Buntaro Fujita

Masayuki Fujita

Masakatsu Fujita

Munehisa Fujita

 

Other publications of authors with the same name

Modeling and analysis of circuit performance of ballistic CNFET., , , and . DAC, page 717-722. ACM, (2006)Patient Context: A New Concept for Gap Model to Understand Patient Satisfaction., and . ICServ, page 151-158. Springer, (2013)Physically unclonable function using initial waveform of ring oscillators on 65 nm CMOS technology., , , , , , , and . CoRR, (2017)D-MRAM cache: enhancing energy efficiency with 3T-1MTJ DRAM/MRAM hybrid memory., , , , , , , , and . DATE, page 1813-1818. EDA Consortium San Jose, CA, USA / ACM DL, (2013)Si Nanocrystal MOSFET with Silicon Nitride Tunnel Insulator for High-rate Random Number Generation., , , , , , and . ISVLSI, page 231-236. IEEE Computer Society, (2006)Novel STT-MRAM-based last level caches for high performance processors using normally-off architectures., , , , , and . ISIC, page 316-319. IEEE, (2014)Compact Fault Recovering Flip-Flop with Adjusting Clock Timing Triggered by Error Detection., and . CICC, page 721-724. IEEE, (2007)Nano-electronics challenge chip designers meet real nano-electronics in 2010s?. DATE, page 431-432. IEEE, (2009)Performance analysis of 3D-IC for multi-core processors in sub-65nm CMOS technologies., , , , and . ISCAS, page 2876-2879. IEEE, (2010)7.2 4Mb STT-MRAM-based cache with memory-access-aware power optimization and write-verify-write / read-modify-write scheme., , , , , , , , , and 3 other author(s). ISSCC, page 132-133. IEEE, (2016)