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Disambiguation of "Matsukawa, Kazuo"

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A 10 MHz BW 50 fJ/conv. continuous time ΔΣ modulator with high-order single opamp integrator using optimization-based design method.

, , , and . VLSIC, page 160-161. IEEE, (2012)

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Kazuo Inoue

Minoru Matsukawa

Kazuo Okohira

Kazuo Yajima

Kazuo Araki

 

Other publications of authors with the same name

A Low Distortion 3rd-Order Continuous-Time Delta-Sigma Modulator for a Worldwide Digital TV-Receiver., , , , , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 95-A (2): 471-478 (2012)A 71dB-SNDR 50MS/s 4.2mW CMOS SAR ADC by SNR enhancement techniques utilizing noise., , , , , , , and . ISSCC, page 272-273. IEEE, (2013)A 4.2 mW 50 MS/s 13 bit CMOS SAR ADC With SNR and SFDR Enhancement Techniques., , , , , , , and . IEEE J. Solid State Circuits, 50 (6): 1372-1381 (2015)A Fifth-Order Continuous-Time Delta-Sigma Modulator With Single-Opamp Resonator., , , , , and . IEEE J. Solid State Circuits, 45 (4): 697-706 (2010)A 10 MHz BW 50 fJ/conv. continuous time ΔΣ modulator with high-order single opamp integrator using optimization-based design method., , , and . VLSIC, page 160-161. IEEE, (2012)A 10.8mA Single Chip Transceiver for 430MHz Narrowband Systems in 0.15µm CMOS., , , , , , , , , and 2 other author(s). ISSCC, page 1480-1489. IEEE, (2006)Design methods for pipeline & delta-sigma A-to-D converters with convex optimization., , , , , , , , , and . ASP-DAC, page 690-695. IEEE, (2009)A 69.8 dB SNDR 3rd-order Continuous Time Delta-Sigma Modulator with an Ultimate Low Power Tuning System for a Worldwide Digital TV-Receiver., , , , , , and . CICC, page 1-4. IEEE, (2010)A 97.99 dB SNDR, 2 kHz BW, 37.1 µW noise-shaping SAR ADC with dynamic element matching and modulation dither effect., , , , and . VLSI Circuits, page 1-2. IEEE, (2016)