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Другие публикации лиц с тем же именем

Data Invalidation Analysis for Scan-Based Debug on Multiple-Clock System Chips., и . J. Electron. Test., 19 (4): 407-416 (2003)A 7-nm 4-GHz Arm¹-Core-Based CoWoS¹ Chiplet Design for High-Performance Computing., , , , , , , , , и 7 other автор(ы). IEEE J. Solid State Circuits, 55 (4): 956-966 (2020)Testing of SoCs with Hierarchical Cores: Common Fallacies, Test Access Optimization, and Test Scheduling., , , и . IEEE Trans. Computers, 58 (3): 409-423 (2009)A Test Time Reduction Algorithm for Test Architecture Design for Core-Based System Chips., и . J. Electron. Test., 19 (4): 425-435 (2003)Accurate measurement of small delay defect coverage of test patterns., , , , и . ITC, стр. 1-10. IEEE Computer Society, (2009)Efficient observation-point insertion for diagnosability enhancement in digital circuits., , , и . ITC, стр. 1-10. IEEE, (2015)Hierarchy-aware and area-efficient test infrastructure design for core-based system chips., , , и . DATE, стр. 285-290. European Design and Automation Association, Leuven, Belgium, (2006)Test challenges in designing complex 3D chips: What in on the horizon for EDA industry?: Designer track.. ICCAD, стр. 273. ACM, (2012)DfT Architecture for 3D-SICs with Multiple Towers., , , и . ETS, стр. 51-56. IEEE Computer Society, (2011)Test scheduling for modular SOCs in an abort-on-fail environment., , , и . ETS, стр. 8-13. IEEE Computer Society, (2005)