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Amber: A 367 GOPS, 538 GOPS/W 16nm SoC with a Coarse-Grained Reconfigurable Array for Flexible Acceleration of Dense Linear Algebra.

A. Carsello, K. Feng, T. Kong, K. Koul, Q. Liu, J. Melchert, G. Nyengele, M. Strange, K. Zhang, A. Nayak, J. Setter, J. Thomas, K. Sreedhar, P. Chen, N. Bhagdikar, Z. Myers, B. D'Agostino, P. Joshi, S. Richardson, R. Bahr, C. Torng, M. Horowitz, and P. Raina. VLSI Technology and Circuits, page 70-71. IEEE, (2022)

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Raghubhai Nayak

Ankita Roy

Sanjeev Kumar Nayak

Arnab Nayak

Sanjit Nayak

Other publications of authors with the same name

Amber: Coarse-Grained Reconfigurable Array-Based SoC for Dense Linear Algebra Acceleration.K. Feng, A. Carsello, T. Kong, K. Koul, Q. Liu, J. Melchert, G. Nyengele, M. Strange, K. Zhang, A. Nayak and 13 other author(s). HCS, page 1-30. IEEE, (2022)Creating an Agile Hardware Design Flow.R. Bahr, C. Barrett, N. Bhagdikar, A. Carsello, R. Daly, C. Donovick, D. Durst, K. Fatahalian, K. Feng, P. Hanrahan and 22 other author(s). DAC, page 1-6. IEEE, (2020)A Framework for Adding Low-Overhead, Fine-Grained Power Domains to CGRAs.A. Nayak, K. Zhang, R. Setaluri, A. Carsello, M. Mann, S. Richardson, R. Bahr, P. Hanrahan, M. Horowitz, and P. Raina. DATE, page 846-851. IEEE, (2020)AHA: An Agile Approach to the Design of Coarse-Grained Reconfigurable Accelerators and Compilers.K. Koul, J. Melchert, K. Sreedhar, L. Truong, G. Nyengele, K. Zhang, Q. Liu, J. Setter, P. Chen, Y. Mei and 23 other author(s). ACM Trans. Embed. Comput. Syst., 22 (2): 35:1-35:34 (March 2023)Interstellar: Using Halide's Scheduling Language to Analyze DNN Accelerators.X. Yang, M. Gao, Q. Liu, J. Setter, J. Pu, A. Nayak, S. Bell, K. Cao, H. Ha, P. Raina and 2 other author(s). ASPLOS, page 369-383. ACM, (2020)ASPLOS 2020 was canceled because of COVID-19..mflowgen: a modular flow generator and ecosystem for community-driven physical design: invited.A. Carsello, J. Thomas, A. Nayak, P. Chen, M. Horowitz, P. Raina, and C. Torng. DAC, page 1339-1342. ACM, (2022)Amber: A 16-nm System-on-Chip With a Coarse- Grained Reconfigurable Array for Flexible Acceleration of Dense Linear Algebra.K. Feng, T. Kong, K. Koul, J. Melchert, A. Carsello, Q. Liu, G. Nyengele, M. Strange, K. Zhang, A. Nayak and 12 other author(s). IEEE J. Solid State Circuits, 59 (3): 947-959 (March 2024)Improving Energy Efficiency of CGRAs with Low-Overhead Fine-Grained Power Domains.A. Nayak, K. Zhang, R. Setaluri, A. Carsello, M. Mann, C. Torng, S. Richardson, R. Bahr, P. Hanrahan, M. Horowitz and 1 other author(s). ACM Trans. Reconfigurable Technol. Syst., 16 (2): 26:1-26:28 (June 2023)Amber: A 367 GOPS, 538 GOPS/W 16nm SoC with a Coarse-Grained Reconfigurable Array for Flexible Acceleration of Dense Linear Algebra.A. Carsello, K. Feng, T. Kong, K. Koul, Q. Liu, J. Melchert, G. Nyengele, M. Strange, K. Zhang, A. Nayak and 13 other author(s). VLSI Technology and Circuits, page 70-71. IEEE, (2022)Enabling Reusable Physical Design Flows with Modular Flow Generators.A. Carsello, J. Thomas, A. Nayak, P. Chen, M. Horowitz, P. Raina, and C. Torng. CoRR, (2021)

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Disambiguation of "Nayak, Ankita"

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Amber: A 367 GOPS, 538 GOPS/W 16nm SoC with a Coarse-Grained Reconfigurable Array for Flexible Acceleration of Dense Linear Algebra.

Please choose a person to relate this publication to

Raghubhai Nayak

Ankita Roy

Sanjeev Kumar Nayak

Arnab Nayak

Sanjit Nayak

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Nayak, Ankita"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Amber: A 367 GOPS, 538 GOPS/W 16nm SoC with a Coarse-Grained Reconfigurable Array for Flexible Acceleration of Dense Linear Algebra.

Please choose a person to relate this publication to

Raghubhai Nayak

Ankita Roy

Sanjeev Kumar Nayak

Arnab Nayak

Sanjit Nayak

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

Amber: A 367 GOPS, 538 GOPS/W 16nm SoC with a Coarse-Grained Reconfigurable Array for Flexible Acceleration of Dense Linear Algebra.