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Disambiguation of "Jeong, Woopyo"

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256 Gb 3 b/Cell V-nand Flash Memory With 48 Stacked WL Layers.

, , , , , , , , , , , , , , , , , , , , , , , , , , , , and . IEEE J. Solid State Circuits, 52 (1): 210-217 (2017)

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Su-Jeong Jeong

Wonrae Jeong

Hyung-Gon Jeong

Hang-Kyun Jeong

Chang-Kyo Jeong

 

Other publications of authors with the same name

Adaptive Supply Voltage for Low-Power Ripple-Carry and Carry-Select Adders., , and . IEICE Trans. Electron., 90-C (4): 865-876 (2007)Hardware architecture and VLSI implementation of a low-power high-performance polyphase channelizer with applications to subband adaptive filtering., , , , , , and . ICASSP (5), page 97-100. IEEE, (2004)256 Gb 3 b/Cell V-nand Flash Memory With 48 Stacked WL Layers., , , , , , , , , and 19 other author(s). IEEE J. Solid State Circuits, 52 (1): 210-217 (2017)A 128 Gb 3b/cell V-NAND Flash Memory With 1 Gb/s I/O Rate., , , , , , , , , and 19 other author(s). IEEE J. Solid State Circuits, 51 (1): 204-212 (2016)7.1 256Gb 3b/cell V-NAND flash memory with 48 stacked WL layers., , , , , , , , , and 20 other author(s). ISSCC, page 130-131. IEEE, (2016)7.2 A 128Gb 3b/cell V-NAND flash memory with 1Gb/s I/O rate., , , , , , , , , and 24 other author(s). ISSCC, page 1-3. IEEE, (2015)Energy-efficient Hardware Architecture and VLSI Implementation of a Polyphase Channelizer with Applications to Subband Adaptive Filtering., , , , , , and . J. Signal Process. Syst., 58 (2): 125-137 (2010)Low Power Adder with Adaptive Supply Voltage., , and . ICCD, page 103-106. IEEE Computer Society, (2003)High-performance low-power dual transition preferentially sized (DTPS) logic., and . IEEE J. Solid State Circuits, 40 (2): 480-484 (2005)A 512-Gb 3-b/Cell 64-Stacked WL 3-D-NAND Flash Memory., , , , , , , , , and 20 other author(s). IEEE J. Solid State Circuits, 53 (1): 124-133 (2018)