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Disambiguation of "Kim, Chulwoo"

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New current-mode sense amplifiers for high density DRAM and PIM architectures.

, , , , and . ISCAS (4), page 938-941. IEEE, (2001)

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Ky ng Kim

Die Artikelstruktur in passiven zweisprachigen Wörterbüchern Deutsch-Koreanisch: Konzeption zur Erstellung eines zweisprachigen Lernerwörterbuchs Deutsch-Koreanisch. Uni Heidelberg, (2008)

Bongcheol Kim

Kim Gerber

Youngsang Kim

Ryong Kim

 

Other publications of authors with the same name

A 32 Gb/s Rx only equalization transceiver with 1-tap speculative FIR and 2-tap direct IIR DFE., , , and . VLSI Circuits, page 1-2. IEEE, (2016)An on-chip soft-start technique of current-mode DC-DC converter for biomedical applications., , , and . APCCAS, page 500-503. IEEE, (2010)Edge-Pursuit Comparator: An Energy-Scalable Oscillator Collapse-Based Comparator With Application in a 74.1 dB SNDR and 20 kS/s 15 b SAR ADC., , , , , , , , and . IEEE J. Solid State Circuits, 52 (4): 1077-1090 (2017)3-Gb/s High-Speed True Random Number Generator Using Common-Mode Operating Comparator and Sampling Uncertainty of D Flip-Flop., , , and . IEEE J. Solid State Circuits, 52 (2): 605-610 (2017)A 2-Gb/s/ch Data-Dependent Swing-Limited On-Chip Signaling for Single-Ended Global I/O in SDRAM., , and . IEEE Trans. Circuits Syst. II Express Briefs, 64-II (10): 1207-1211 (2017)A 7.5-Gb/s Referenceless Transceiver With Adaptive Equalization and Bandwidth-Shifting Technique for Ultrahigh-Definition Television in a 0.13- µm CMOS Process., , , and . IEEE Trans. Circuits Syst. II Express Briefs, 61-II (11): 865-869 (2014)A 140-Mb/s to 1.82-Gb/s Continuous-Rate Embedded Clock Receiver for Flat-Panel Displays., , , and . IEEE Trans. Circuits Syst. II Express Briefs, 56-II (10): 773-777 (2009)A 1-mW Solar-Energy-Harvesting Circuit Using an Adaptive MPPT With a SAR and a Counter., , , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 60-II (6): 331-335 (2013)A 90.2% Peak Efficiency Multi-Input Single-Inductor Multi-Output Energy Harvesting Interface With Double-Conversion Rejection Technique and Buck-Based Dual-Conversion Mode., , , , , and . IEEE J. Solid State Circuits, 56 (3): 961-971 (2021)A 7ps-Jitter 0.053mm2 Fast-Lock ADDLL with Wide-Range and High-Resolution All-Digital DCC., , , , , and . ISSCC, page 184-595. IEEE, (2007)