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Technology Mapping for Speed-Independent Circuits: Decomposition and Resynthesis.

, , , , and . ASYNC, page 240-253. IEEE Computer Society, (1997)

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Quasi-static Scheduling for Concurrent Architectures., , , , and . Fundam. Informaticae, 62 (2): 171-196 (2004)A region-based theory for state assignment in speed-independent circuits., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 16 (8): 793-812 (1997)Testing redundant asynchronous circuits by variable phase splitting., , and . EURO-DAC, page 328-333. IEEE Computer Society, (1994)Design of a pseudo-log image transform hardware accelerator in a high-level synthesis-based memory management framework., , , and . J. Electronic Imaging, 23 (5): 053012 (2014)Design of Asynchronous Controllers with Delay Insensitive Interface., , , , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 85-A (12): 2577-2585 (2002)Software Development for High-Performance, Reconfigurable, Embedded Multimedia Systems., , and . IEEE Des. Test Comput., 22 (1): 28-38 (2005)Timed Shannon Circuits: A Power-Efficient Design Style and Synthesis Tool., , , and . DAC, page 254-260. ACM Press, (1995)Solving the State Assignment Problem for Signal Transition Graphs., , , and . DAC, page 568-572. IEEE Computer Society Press, (1992)Enabling adaptability through elastic clocks., , and . DAC, page 8-10. ACM, (2009)A Fully-Automated Desynchronization Flow for Synchronous Circuits., , , and . DAC, page 982-985. IEEE, (2007)