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Interstellar: Using Halide's Scheduling Language to Analyze DNN Accelerators., , , , , , , , , и 2 other автор(ы). ASPLOS, стр. 369-383. ACM, (2020)ASPLOS 2020 was canceled because of COVID-19..Compiling Halide Programs to Push-Memory Accelerators., , , , , , , , , и 1 other автор(ы). CoRR, (2021)Low-overhead implementation of logic encryption using gate replacement techniques., , , , и . ISQED, стр. 257-263. IEEE, (2017)Hardware Trojan Detection in Third-Party Digital Intellectual Property Cores by Multilevel Feature Analysis., , , , , , , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 37 (7): 1370-1383 (2018)Unified Buffer: Compiling Image Processing and Machine Learning Applications to Push-Memory Accelerators., , , , , , , и . ACM Trans. Archit. Code Optim., 20 (2): 26:1-26:26 (июня 2023)AHA: An Agile Approach to the Design of Coarse-Grained Reconfigurable Accelerators and Compilers., , , , , , , , , и 23 other автор(ы). ACM Trans. Embed. Comput. Syst., 22 (2): 35:1-35:34 (марта 2023)FASTrust: Feature analysis for third-party IP trust verification., , , , , , , и . ITC, стр. 1-10. IEEE, (2015)Amber: A 16-nm System-on-Chip With a Coarse- Grained Reconfigurable Array for Flexible Acceleration of Dense Linear Algebra., , , , , , , , , и 12 other автор(ы). IEEE J. Solid State Circuits, 59 (3): 947-959 (марта 2024)Automating System Configuration., , , , , , и . FMCAD, стр. 102-111. IEEE, (2021)Amber: A 367 GOPS, 538 GOPS/W 16nm SoC with a Coarse-Grained Reconfigurable Array for Flexible Acceleration of Dense Linear Algebra., , , , , , , , , и 13 other автор(ы). VLSI Technology and Circuits, стр. 70-71. IEEE, (2022)