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Disambiguation of "Kapoor, Hemangee K."

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Towards Analysing the Effect of Hybrid Caches on the Temperature of Tiled Chip Multi-Processors.

, , , , and . iSES, page 52-57. IEEE, (2018)

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Rishi Kapoor

Varun Kapoor

Pridhee Kapoor

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Kalpesh Kapoor

 

Other publications of authors with the same name

Modelling and analysis of wireless communication over Networks-on-Chip., and . VDAT, page 1-6. IEEE, (2014)A Framework for Block Placement, Migration, and Fast Searching in Tiled-DNUCA Architecture., and . ACM Trans. Design Autom. Electr. Syst., 22 (1): 4:1-4:26 (2016)Performance linked dynamic cache tuning: A static energy reduction approach in tiled CMPs., and . Microprocess. Microsystems, (2017)Reinforcement Learning Based Refresh Optimized Volatile STT-RAM Cache., and . ISVLSI, page 222-227. IEEE, (2020)Restricting writes for energy-efficient hybrid cache in multi-core architectures., and . VLSI-SoC, page 1-6. IEEE, (2016)DidaSel: dirty data based selection of VC for effective utilization of NVM buffers in on-chip interconnects., , and . ISLPED, page 151-156. ACM, (2020)Dimming Hybrid Caches to Assist in Temperature Control of Chip MultiProcessors., , , and . ACM Great Lakes Symposium on VLSI, page 487-492. ACM, (2020)SRS-Mig: Selection and Run-time Scheduling of page Migration for improved response time in hybrid PCM-DRAM memories., , , and . ACM Great Lakes Symposium on VLSI, page 217-222. ACM, (2022)AGRAS: Aging and memory request rate aware scheduler for PCM memories., and . ISQED, page 1-8. IEEE, (2023)DAMUS: Dynamic Allocation based on Write Frequency in MUlti-Retention STT-RAM based Last Level Caches., , , , and . ISQED, page 469-475. IEEE, (2021)