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A scalable and efficient methodology to extract two node bridges from large industrial circuits.

, and . ITC, page 750-759. IEEE Computer Society, (2000)

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A scalable and efficient methodology to extract two node bridges from large industrial circuits., and . ITC, page 750-759. IEEE Computer Society, (2000)Layout Analysis to Extract Open Nets Caused by Systematic Failure Mechanisms., , , , , and . VTS, page 367-372. IEEE Computer Society, (2002)A Novel Algorithm for Multi-Node Bridge Analysis of Large VLSI Circuits., and . VLSI Design, page 333-338. IEEE Computer Society, (2001)Logic proximity bridges., , , and . ITC, page 10. IEEE Computer Society, (2005)Experimental Evaluation of Scan Tests for Bridges., , , , and . ITC, page 509-518. IEEE Computer Society, (2002)Extraction of two-node bridges from large industrial circuits., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 23 (3): 433-439 (2004)On Modeling Cross-Talk Faults., , , and . DATE, page 10490-10495. IEEE Computer Society, (2003)A novel algorithm to extract two-node bridges., , and . DAC, page 790-793. ACM, (2000)Test Challenges in Nanometer Technologies., , , and . J. Electron. Test., 17 (3-4): 209-218 (2001)Physical Design Trends and Layout-Based Fault Modeling., , , and . VLSI Design, page 6-8. IEEE Computer Society, (2004)