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An 11b 3.6GS/s time-interleaved SAR ADC in 65nm CMOS.

E. Janssen, K. Doris, A. Zanikopoulos, A. Murroni, G. van der Weide, Y. Lin, L. Alvado, F. Darthenay, and Y. Fregeais. ISSCC, page 464-465. IEEE, (2013)

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A flexible ADC approach for mixed-signal SoC platforms.A. Zanikopoulos, P. Harpe, H. Hegt, and A. van Roermund. ISCAS (5), page 4839-4842. IEEE, (2005)Analog Calibration of Mismatches in an Open-Loop Track-and-Hold Circuit for Time-Interleaved ADCs.P. Harpe, A. Zanikopoulos, H. Hegt, and A. van Roermund. ISCAS, page 1951-1954. IEEE, (2007)Digital post-correction of front-end track-and-hold circuits in ADCs.P. Harpe, A. Zanikopoulos, H. Hegt, and A. van Roermund. ISCAS, IEEE, (2006)Power Optimization for Pipelined ADCs with Open-Loop Residue Amplifiers.A. Zanikopoulos, P. Harpe, H. Hegt, and A. van Roermund. ICECS, page 132-135. IEEE, (2006)A 480mW 2.6GS/s 10b 65nm CMOS time-interleaved ADC with 48.5dB SNDR up to Nyquist.K. Doris, E. Janssen, C. Nani, A. Zanikopoulos, and G. van der Weide. ISSCC, page 180-182. IEEE, (2011)Design of the Basic Building Block of a High-Speed Flexible and Modular Pipelined ADC.A. Zanikopoulos, P. Harpe, H. Hegt, and A. van Roermund. ISCAS, page 3876-3879. IEEE, (2007)Digital self-correction of time-interleaved ADCs.P. Harpe, A. Zanikopoulos, and A. van Roermund. ISCAS (6), page 5541-5544. IEEE, (2005)An 11b 1GS/s ADC with parallel sampling architecture to enhance SNDR for multi-carrier signals.Y. Lin, K. Doris, E. Janssen, A. Zanikopoulos, A. Murroni, G. van der Weide, H. Hegt, and A. van Roermund. ESSCIRC, page 121-124. IEEE, (2013)Smart AD and DA converters.A. van Roermund, H. Hegt, P. Harpe, G. Radulov, A. Zanikopoulos, K. Doris, and P. Quinn. ISCAS (4), page 4062-4065. IEEE, (2005)A 480 mW 2.6 GS/s 10b Time-Interleaved ADC With 48.5 dB SNDR up to Nyquist in 65 nm CMOS.K. Doris, E. Janssen, C. Nani, A. Zanikopoulos, and G. van der Weide. IEEE J. Solid State Circuits, 46 (12): 2821-2833 (2011)

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An 11b 3.6GS/s time-interleaved SAR ADC in 65nm CMOS.

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copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML An 11b 3.6GS/s time-interleaved SAR ADC in 65nm CMOS.

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An 11b 3.6GS/s time-interleaved SAR ADC in 65nm CMOS.