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HESSLE-FREE: <u>He</u>terogeneou<u>s</u> <u>S</u>ystems <u>Le</u>veraging <u>F</u>uzzy Control for <u>R</u>untim<u>e</u> Resourc<u>e</u> Management.

, , , , and . ACM Trans. Embed. Comput. Syst., 18 (5s): 74:1-74:19 (2019)

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Customizing Software Toolkits for Embedded Systems-On-Chip., , and . DIPES, volume 189 of IFIP Conference Proceedings, page 87-98. Kluwer, (2000)Novel Brain-Derived Algorithms Scale Linearly with Number of Processing Elements., , , , , , , and . PARCO, volume 15 of Advances in Parallel Computing, page 767-776. IOS Press, (2007)Data Partitioning Techniques for Partially Protected Caches to Reduce Soft Error Induced Failures., , , and . DIPES, volume 271 of IFIP, page 213-225. Springer, (2008)Generic Pipelined Processor Modeling and High Performance Cycle-Accurate Simulator Generation, and . CoRR, (2007)ISEGEN: Generation of High-Quality Instruction Set Extensions by Iterative Improvement, , , , and . CoRR, (2007)A Unified code generation approach using mutation scheduling., , and . Code Generation for Embedded Processors, page 203-218. Kluwer, (1994)A hypergraph-based model for port allocation on multiple-register-file VLIW architectures., , and . Int. J. Parallel Program., 23 (6): 499-513 (1995)Energy-Aware Adaptations for End-to-End Videostreaming to Mobile Handheld Devices., , , , and . Ultra Low-Power Electronics and Design, Kluwer / Springer, (2004)Mapping Spiking Neural Networks to Neuromorphic Hardware., , , , , , , , , and . CoRR, (2019)Generic Processor Modeling for Automatically Generating Very Fast Cycle-Accurate Simulators., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 25 (12): 2904-2918 (2006)