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Deceptive Logic Locking for Hardware Integrity Protection Against Machine Learning Attacks., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 41 (6): 1716-1729 (2022)NeuroHammer: Inducing Bit-Flips in Memristive Crossbar Memories., , , , , , , , and . CoRR, (2021)Architecture, Dataflow and Physical Design Implications of 3D-ICs for DNN-Accelerators., , , , , , and . CoRR, (2020)QTFlow: Quantitative Timing-Sensitive Information Flow for Security-Aware Hardware Design on RTL., , , , , , and . CoRR, (2024)A Survey of Neuromorphic Computing-in-Memory: Architectures, Simulators, and Security., , and . IEEE Des. Test, 39 (2): 90-99 (2022)Optimized Communication Architecture of MPSoCs with a Hardware Scheduler: A System-Level Analysis., , , , , , and . Int. J. Embed. Real Time Commun. Syst., 2 (3): 1-20 (2011)Frequency-Aware ESL Power Estimation for ARM Cortex-A9 Using a Black Box Processor Model., , , , and . ACM Trans. Embed. Comput. Syst., 16 (1): 26:1-26:26 (2016)Modelling Machine Learning Components for Mapping and Scheduling of AUTOSAR Runnables., , and . ISSRE, page 127-137. IEEE, (2020)Automatic Energy-Minimized HW/SW Partitioning for FPGA-Accelerated MPSoCs., , , , , , and . IEEE Embed. Syst. Lett., 11 (3): 93-96 (2019)AMAIX: A Generic Analytical Model for Deep Learning Accelerators., , , , and . SAMOS, volume 12471 of Lecture Notes in Computer Science, page 36-51. Springer, (2020)