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A Voltage-Controlled, Oscillation-Based ADC Design for Computation-in-Memory Architectures Using Emerging ReRAMs.

, , , , , , , , , , and . ACM J. Emerg. Technol. Comput. Syst., 18 (2): 32:1-32:25 (2022)

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Variability-Aware Modeling of Filamentary Oxide-Based Bipolar Resistive Switching Cells Using SPICE Level Compact Models., , , , , , , , and . IEEE Trans. Circuits Syst., 67-I (12): 4618-4630 (2020)Experimental Validation of Memristor-Aided Logic Using 1T1R TaOx RRAM Crossbar Array., , , , , , , , , and 3 other author(s). CoRR, (2023)Implementation of Multinary Łukasiewicz Logic Using Memristive Devices., , , and . ISCAS, page 1-5. IEEE, (2021)Analysis of VMM Operations on 1S1R Crossbar Arrays and the Influence of Wire Resistances., , , , and . ISCAS, page 91-95. IEEE, (2022)Realization of Memristor-aided Logic Gates with Analog Memristive Devices., , , , , , , and . MOCAST, page 1-4. IEEE, (2022)Ternary Łukasiewicz logic using memristive devices., , , , , , , and . Neuromorph. Comput. Eng., 3 (4): 44001 (December 2023)Reliability aspects of binary vector-matrix-multiplications using ReRAM devices., , , , , , , , , and . Neuromorph. Comput. Eng., 2 (3): 34001 (2022)Bit slicing approaches for variability aware ReRAM CIM macros., , , , and . it Inf. Technol., 65 (1-2): 3-12 (May 2023)Eliminating Capacitive Sneak Paths in Associative Capacitive Networks based on Complementary Resistive Switches for In-Memory Computing., , , , , and . IMW, page 1-4. IEEE, (2023)MNEMOSENE: Tile Architecture and Simulator for Memristor-based Computation-in-memory., , , , , , , , and . ACM J. Emerg. Technol. Comput. Syst., 18 (3): 44:1-44:24 (2022)