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Three-Dimensional 128 Gb MLC Vertical nand Flash Memory With 24-WL Stacked Layers and 50 MB/s High-Speed Programming.

, , , , , , , , , , , , , , , , , , , , , , , , , , , , , and . IEEE J. Solid State Circuits, 50 (1): 204-213 (2015)

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7.2 A 128Gb 3b/cell V-NAND flash memory with 1Gb/s I/O rate., , , , , , , , , and 24 other author(s). ISSCC, page 1-3. IEEE, (2015)A 7MB/s 64Gb 3-bit/cell DDR NAND flash memory in 20nm-node technology., , , , , , , , , and 19 other author(s). ISSCC, page 212-213. IEEE, (2011)Three-Dimensional 128 Gb MLC Vertical nand Flash Memory With 24-WL Stacked Layers and 50 MB/s High-Speed Programming., , , , , , , , , and 20 other author(s). IEEE J. Solid State Circuits, 50 (1): 204-213 (2015)13.1 A 1Tb 4b/cell NAND Flash Memory with tPROG=2ms, tR=110µs and 1.2Gb/s High-Speed IO Rate., , , , , , , , , and 35 other author(s). ISSCC, page 218-220. IEEE, (2020)A new 3-bit programming algorithm using SLC-to-TLC migration for 8MB/s high performance TLC NAND flash memory., , , , , , , , , and 7 other author(s). VLSIC, page 132-133. IEEE, (2012)2.4 ATOMUS: A 5nm 32TFLOPS/128TOPS ML System-on-Chip for Latency Critical Applications., , , , , , , , , and 56 other author(s). ISSCC, page 42-44. IEEE, (2024)19.5 Three-dimensional 128Gb MLC vertical NAND Flash-memory with 24-WL stacked layers and 50MB/s high-speed programming., , , , , , , , , and 35 other author(s). ISSCC, page 334-335. IEEE, (2014)SENIN: An energy-efficient sparse neuromorphic system with on-chip learning., , , and . ISLPED, page 1-6. IEEE, (2017)A 1Tb 3b/Cell 8th-Generation 3D-NAND Flash Memory with 164MB/s Write Throughput and a 2.4Gb/s Interface., , , , , , , , , and 24 other author(s). ISSCC, page 136-137. IEEE, (2022)A 128 Gb 3b/cell V-NAND Flash Memory With 1 Gb/s I/O Rate., , , , , , , , , and 19 other author(s). IEEE J. Solid State Circuits, 51 (1): 204-212 (2016)