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%0 Journal Article
%1 journals/pieee/CalhounCLMPRS08
%A Calhoun, Benton H.
%A Cao, Yu
%A Li, Xin
%A Mai, Ken
%A Pileggi, Lawrence T.
%A Rutenbar, Rob A.
%A Shepard, Kenneth L.
%D 2008
%J Proc. IEEE
%K dblp
%N 2
%P 343-365
%T Digital Circuit Design Challenges and Opportunities in the Era of Nanoscale CMOS.
%U http://dblp.uni-trier.de/db/journals/pieee/pieee96.html#CalhounCLMPRS08
%V 96
@article{journals/pieee/CalhounCLMPRS08,
added-at = {2024-03-22T00:00:00.000+0100},
author = {Calhoun, Benton H. and Cao, Yu and Li, Xin and Mai, Ken and Pileggi, Lawrence T. and Rutenbar, Rob A. and Shepard, Kenneth L.},
biburl = {https://www.bibsonomy.org/bibtex/233e12f00bf81fb8f18d4b1c10dd033a2/dblp},
ee = {https://doi.org/10.1109/JPROC.2007.911072},
interhash = {7b2709da36094ba0fb93f952f99db281},
intrahash = {33e12f00bf81fb8f18d4b1c10dd033a2},
journal = {Proc. IEEE},
keywords = {dblp},
number = 2,
pages = {343-365},
timestamp = {2024-04-09T04:37:47.000+0200},
title = {Digital Circuit Design Challenges and Opportunities in the Era of Nanoscale CMOS.},
url = {http://dblp.uni-trier.de/db/journals/pieee/pieee96.html#CalhounCLMPRS08},
volume = 96,
year = 2008
}
