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Disambiguation of "Papaefthymiou, Marios C."

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Practical repeater insertion for low power: what repeater library do we need?

, , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 25 (5): 917-924 (2006)

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Marios Strapatsakis

Spyros Papaefthymiou

Marios Psychogios

Marios Papakyriacou

Marios Paulides

 

Other publications of authors with the same name

A 5.5GS/s 28mW 5-bit flash ADC with resonant clock distribution., , and . ESSCIRC, page 155-158. IEEE, (2011)Incorporation of input glitches into power macromodeling., and . ISCAS (4), page 846-849. IEEE, (2002)Maximizing Performance by Retiming and Clock Skew Scheduling., , and . DAC, page 231-236. ACM Press, (1999)Block-based multiperiod dynamic memory design for low data-retention power., and . IEEE Trans. Very Large Scale Integr. Syst., 11 (6): 1006-1018 (2003)Design of a 20-mb/s 256-state Viterbi decoder., and . IEEE Trans. Very Large Scale Integr. Syst., 11 (6): 965-975 (2003)Practical repeater insertion for low power: what repeater library do we need?, , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 25 (5): 917-924 (2006)Retiming edge-triggered circuits under general delay models., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 16 (12): 1393-1408 (1997)Resonant-Clock Latch-Based Design., , and . IEEE J. Solid State Circuits, 43 (4): 864-873 (2008)A 0.23mW Heterogeneous Deep-Learning Processor Supporting Dynamic Execution of Conditional Neural Networks., , and . ESSCIRC, page 162-165. IEEE, (2018)Experimental Evaluation of Resonant Clock Distribution., , and . ISVLSI, page 135-140. IEEE Computer Society, (2004)