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A 5-Gbps 1.7 pJ/bit ditherless CDR with optimal phase interval detection.

, , , and . CICC, page 1-4. IEEE, (2012)

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Fast and accurate event-driven simulation of mixed-signal systems with data supplementation., , , and . CICC, page 1-4. IEEE, (2011)22.3 A 128Gb 8-High 512GB/s HBM2E DRAM with a Pseudo Quarter Bank Structure, Power Dispersion and an Instruction-Based At-Speed PMBIST., , , , , , , , , and 27 other author(s). ISSCC, page 334-336. IEEE, (2020)Pseudo-Linear Analysis of Bang-Bang Controlled Timing Circuits., and . IEEE Trans. Circuits Syst. I Regul. Pap., 60-I (6): 1381-1394 (2013)A 192-Gb 12-High 896-GB/s HBM3 DRAM With a TSV Auto-Calibration Scheme and Machine-Learning-Based Layout Optimization., , , , , , , , , and 29 other author(s). IEEE J. Solid State Circuits, 58 (1): 256-269 (2023)A 2.3-mW, 5-Gb/s Low-Power Decision-Feedback Equalizer Receiver Front-End and its Two-Step, Minimum Bit-Error-Rate Adaptation Algorithm., , , , , , and . IEEE J. Solid State Circuits, 48 (11): 2693-2704 (2013)A 2.5-V, 160-μJ-output piezoelectric energy harvester and power management IC for batteryless wireless switch (BWS) applications., , , , and . VLSIC, page 282-. IEEE, (2015)Design and Analysis of Energy-Efficient Single-Pulse Piezoelectric Energy Harvester and Power Management IC for Battery-Free Wireless Remote Switch Applications., , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 65-I (1): 366-379 (2018)Time slot optimization algorithm for multisource energy harvesting systems., , , , and . ESSCIRC, page 499-502. IEEE, (2016)An event-driven simulation methodology for integrated switching power supplies in SystemVerilog., , and . DAC, page 137:1-137:7. ACM, (2013)A 4×40 Gb/s quad-lane CDR with shared frequency tracking and data dependent jitter filtering., , , , , , , , , and 4 other author(s). VLSIC, page 1-2. IEEE, (2014)