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Disambiguation of "Koyanagi, Yoichi"

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A 56-Gb/s receiver front-end with a CTLE and 1-tap DFE in 20-nm CMOS.

, , , , , , , , and . VLSIC, page 1-2. IEEE, (2014)

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Yoichi Kiuchi

Yoichi Otani

Yoichi Ishikawa

 

Other publications of authors with the same name

Fault Tolerant Neural Networks in Optimization Problems., and . FTCS, page 412-418. IEEE Computer Society, (1992)Design of Neural Networks to Tolerate the Mixture of Two Types of Faults., and . FTCS, page 268-277. IEEE Computer Society, (1993)3.5 A 56Gb/s NRZ-electrical 247mW/lane serial-link transceiver in 28nm CMOS., , , , , , , , , and 7 other author(s). ISSCC, page 64-65. IEEE, (2016)A 56-Gb/s receiver front-end with a CTLE and 1-tap DFE in 20-nm CMOS., , , , , , , , and . VLSIC, page 1-2. IEEE, (2014)32Gb/s data-interpolator receiver with 2-tap DFE in 28nm CMOS., , , , , , , , , and 1 other author(s). ISSCC, page 36-37. IEEE, (2013)32Gb/s 28nm CMOS time-interleaved transmitter compatible with NRZ receiver with DFE., , , , , , , , and . ISSCC, page 40-41. IEEE, (2013)22.7 4×25.78Gb/s retimer ICs for optical links in 0.13μm SiGe BiCMOS., , , , , , , , and . ISSCC, page 1-3. IEEE, (2015)A 10th generation 16-core SPARC64 processor for mission-critical UNIX server., , , , , , , , , and 4 other author(s). ISSCC, page 60-61. IEEE, (2013)24 to 34-Gb/s ×4 multi-rate VCSEL-based optical transceiver with referenceless CDR., , , , , , , , and . OFC, page 1-3. IEEE, (2016)A 4-channel 10.3Gb/s transceiver with adaptive phase equalizer for 4-to-41dB loss PCB channel., , , , , , , , , and . ISSCC, page 346-348. IEEE, (2011)