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Charge-based fault simulation for CMOS network breaks.

, , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 15 (12): 1555-1567 (1996)

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Extraction and Simulation of Realistic CMOS Faults Using Inductive Fault Analysis., and . ITC, page 475-484. IEEE Computer Society, (1988)Microprocessor Interfacing and the 68000: Peripherals and systems: Clements, A Wiley and Sons Ltd, Chichester, UK (1989) £39.95 pp 446.. Microprocess. Microsystems, 13 (10): 674 (1989)Oscillation and sequential behavior caused by opens in the routing in digital CMOS circuits., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 17 (11): 1200-1210 (1998)On state reduction of incompletely specified finite state machines., and . Comput. Electr. Eng., 33 (1): 58-69 (2007)Carafe: an inductive fault analysis tool for CMOS VLSI circuits., and . VTS, page 92-98. IEEE Computer Society, (1993)Physical design for testability for bridges in CMOS circuits.. VTS, page 290-295. IEEE Computer Society, (1993)A methodolgy for characterizing cell testability., and . VTS, page 384-390. IEEE Computer Society, (1997)Using Temporal Constraints for Eliminating Crosstalk Candidates for Design and Test., and . VTS, page 80-85. IEEE Computer Society, (1999)A Systematic DFT Procedure for Library Cells., , and . VTS, page 460-466. IEEE Computer Society, (1999)Oscillation and Sequential Behavior Caused by Interconnect Opens in Digital CMOS Circuits., and . ITC, page 597-606. IEEE Computer Society, (1997)