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Layout-Oriented Defect Set Reduction for Fast Circuit Simulation in Cell-Aware Test.

H. Liu, B. Lin, and C. Wu. ATS, page 156-160. IEEE Computer Society, (2016)

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Lin Yang

Yang Lin

Jen-Yang Lin

Xiao-bing Yang-Benckendorff

Other publications of authors with the same name

Supporting Multimedia Applications in Home Networks using SIP and SLP.M. Chen, B. Lin, and W. Weng. DCNET/OPTICS, page 19-24. SciTePress, (2010)Test Cost Reduction Methodology for InFO Wafer-Level Chip-Scale Package.K. Wang, B. Lin, C. Wu, M. Lee, H. Chen, H. Lin, C. Peng, and M. Wang. IEEE Des. Test, 34 (3): 50-58 (2017)Efficient probing schemes for fine-pitch pads of InFO wafer-level chip-scale package.Y. Huang, B. Lin, C. Wu, M. Lee, H. Chen, H. Lin, C. Peng, and M. Wang. DAC, page 58:1-58:6. ACM, (2016)Layout-Oriented Defect Set Reduction for Fast Circuit Simulation in Cell-Aware Test.H. Liu, B. Lin, and C. Wu. ATS, page 156-160. IEEE Computer Society, (2016)A Built-Off Self-Repair Scheme for Channel-Based 3D Memories.H. Liu, B. Lin, C. Wu, W. Chiang, M. Lee, H. Lin, C. Peng, and M. Wang. IEEE Trans. Computers, 66 (8): 1293-1301 (2017)A Local Parallel Search Approach for Memory Failure Pattern Identification.B. Lin, C. Wu, M. Lee, H. Lin, C. Peng, and M. Wang. IEEE Trans. Computers, 65 (3): 770-780 (2016)Controller Architecture for Low-Power, Low-Latency DRAM With Built-in Cache.Z. Liu, H. Shih, B. Lin, and C. Wu. IEEE Des. Test, 34 (2): 69-78 (2017)Configurable Cubical Redundancy Schemes for Channel-Based 3-D DRAM Yield Improvement.B. Lin, W. Chiang, C. Wu, M. Lee, H. Lin, C. Peng, and M. Wang. IEEE Des. Test, 33 (2): 30-39 (2016)Exploration Methodology for 3D Memory Redundancy Architectures under Redundancy Constraints.B. Lin, M. Lee, and C. Wu. Asian Test Symposium, page 1-6. IEEE Computer Society, (2013)Redundancy architectures for channel-based 3D DRAM yield improvement.B. Lin, W. Chiang, C. Wu, M. Lee, H. Lin, C. Peng, and M. Wang. ITC, page 1-7. IEEE Computer Society, (2014)

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Disambiguation of "Lin, Bing-Yang"

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Layout-Oriented Defect Set Reduction for Fast Circuit Simulation in Cell-Aware Test.

Please choose a person to relate this publication to

Lin Yang

Lin Yang

Yang Lin

Jen-Yang Lin

Xiao-bing Yang-Benckendorff

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Lin, Bing-Yang"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Layout-Oriented Defect Set Reduction for Fast Circuit Simulation in Cell-Aware Test.

Please choose a person to relate this publication to

Lin Yang

Lin Yang

Yang Lin

Jen-Yang Lin

Xiao-bing Yang-Benckendorff

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

Layout-Oriented Defect Set Reduction for Fast Circuit Simulation in Cell-Aware Test.