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Disambiguation of "Peng, Xiaochen"

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Design Guidelines of RRAM based Neural-Processing-Unit: A Joint Device-Circuit-Algorithm Analysis.

, , , , , , , and . DAC, page 140. ACM, (2019)

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Xiaochen Hu

Xiaochen Lian

Changgeng Peng

Xiao-Wei Peng

Martin Peng

 

Other publications of authors with the same name

Achieving High In Situ Training Accuracy and Energy Efficiency with Analog Non-Volatile Synaptic Devices., , , , and . ACM Trans. Design Autom. Electr. Syst., 27 (4): 37:1-37:19 (2022)Compute-in-Memory: From Device Innovation to 3D System Integration., , , , , , , and . ESSDERC, page 21-28. IEEE, (2021)A Runtime Reconfigurable Design of Compute-in-Memory based Hardware Accelerator., , , , and . DATE, page 932-937. IEEE, (2021)NeuroSim: A Circuit-Level Macro Model for Benchmarking Neuro-Inspired Architectures in Online Learning., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 37 (12): 3067-3080 (2018)Benchmark Framework for 2-D/3-D Integrated Compute-in-Memory Based Machine Learning Accelerator.. Georgia Institute of Technology, Atlanta, GA, USA, (2022)base-search.net (ftgeorgiatech:oai:smartech.gatech.edu:1853/66465).XOR-CIM: Compute-In-Memory SRAM Architecture with Embedded XOR Encryption., , , , and . ICCAD, page 77:1-77:6. IEEE, (2020)Overcoming Challenges for Achieving High in-situ Training Accuracy with Emerging Memories., , , , and . DATE, page 1025-1030. IEEE, (2020)XNOR-RRAM: A scalable and parallel resistive synaptic architecture for binary neural networks., , , , , and . DATE, page 1423-1428. IEEE, (2018)Design Guidelines of RRAM based Neural-Processing-Unit: A Joint Device-Circuit-Algorithm Analysis., , , , , , , and . DAC, page 140. ACM, (2019)Parallelizing SRAM arrays with customized bit-cell for binary neural networks., , , , , , , , and . DAC, page 21:1-21:6. ACM, (2018)