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A 2.6 mW/Gbps 12.5 Gbps RX With 8-Tap Switched-Capacitor DFE in 32 nm CMOS., , , , , , , , , and 3 other author(s). IEEE J. Solid State Circuits, 47 (4): 897-910 (2012)Adaptive high-speed and ultra-low power optical interconnect for data center communications., , , , , , , and . ICTON, page 1-4. IEEE, (2017)F5: Enabling New System Architectures with 2.5D, 3D, and Chiplets., , , , , and . ISSCC, page 529-532. IEEE, (2021)Analysis of parameter-independent PLLs with bang-bang phase-detectors., , , and . ICECS, page 299-302. IEEE, (1998)A 5.7mW/Gb/s 24-to-240Ω 1.6Gb/s thin-oxide DDR transmitter with 1.9-to-7.6V/ns clock-feathering slew-rate control in 22nm CMOS., , , , , , , , and . ISSCC, page 310-311. IEEE, (2013)23.6 A 30Gb/s 0.8pJ/b 14nm FinFET receiver data-path., , , , , , , , , and 1 other author(s). ISSCC, page 408-409. IEEE, (2016)A 24-to-72GS/s 8b time-interleaved SAR ADC with 2.0-to-3.3pJ/conversion and >30dB SNDR at nyquist in 14nm CMOS FinFET., , , , , , , , , and . ISSCC, page 358-360. IEEE, (2018)Design Techniques for High-Speed Multi-Level Viterbi Detectors and Trellis-Coded-Modulation Decoders., , , , , , , , , and 3 other author(s). IEEE Trans. Circuits Syst. I Regul. Pap., 65-I (10): 3529-3542 (2018)Low-Complexity Adaptive Equalization for High-Speed Chip-to-Chip Communication Paths by Zero-Forcing of Jitter Components., , and . IEEE Trans. Commun., 54 (9): 1554-1557 (2006)A 4.5mW/Gb/s 6.4Gb/s 22+1-lane source-synchronous link rx core with optional cleanup PLL in 65nm CMOS., , , , , , and . ISSCC, page 160-161. IEEE, (2010)