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Disambiguation of "Menolfi, Christian"

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23.6 A 30Gb/s 0.8pJ/b 14nm FinFET receiver data-path.

, , , , , , , , , , and . ISSCC, page 408-409. IEEE, (2016)

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Christian Ivo Menolfi

Christian Christian

Christian Winter

Gold-katalysierte Cycloisomerisierung funktionalisierter Allene und Anwendung in der Naturstoffsynthese. TU Dortmund, (2009)

Christian Helbig

Synthese und Charakterisierung von metallorganischen Bronzen. Uni Augsburg, (2009)

Christian Schüller

Automatisierte Feedbackgenerierung in der benutzerzentrierten Softwareentwicklung am Beispiel mobiler Anwendungen. TU München, (2009)
 

Other publications of authors with the same name

A 2.6 mW/Gbps 12.5 Gbps RX With 8-Tap Switched-Capacitor DFE in 32 nm CMOS., , , , , , , , , and 3 other author(s). IEEE J. Solid State Circuits, 47 (4): 897-910 (2012)Design Techniques for High-Speed Multi-Level Viterbi Detectors and Trellis-Coded-Modulation Decoders., , , , , , , , , and 3 other author(s). IEEE Trans. Circuits Syst. I Regul. Pap., 65-I (10): 3529-3542 (2018)A 24-to-72GS/s 8b time-interleaved SAR ADC with 2.0-to-3.3pJ/conversion and >30dB SNDR at nyquist in 14nm CMOS FinFET., , , , , , , , , and . ISSCC, page 358-360. IEEE, (2018)A 5.7mW/Gb/s 24-to-240Ω 1.6Gb/s thin-oxide DDR transmitter with 1.9-to-7.6V/ns clock-feathering slew-rate control in 22nm CMOS., , , , , , , , and . ISSCC, page 310-311. IEEE, (2013)23.6 A 30Gb/s 0.8pJ/b 14nm FinFET receiver data-path., , , , , , , , , and 1 other author(s). ISSCC, page 408-409. IEEE, (2016)A 60-Gb/s 1.9-pJ/bit NRZ Optical Receiver With Low-Latency Digital CDR in 14-nm CMOS FinFET., , , , , , , , , and 7 other author(s). IEEE J. Solid State Circuits, 53 (4): 1227-1237 (2018)A 64-Gb/s 1.4-pJ/b NRZ Optical Receiver Data-Path in 14-nm CMOS FinFET., , , , , , , , , and 7 other author(s). IEEE J. Solid State Circuits, 52 (12): 3458-3473 (2017)A low-noise CMOS instrumentation amplifier for thermoelectric infrared detectors., and . IEEE J. Solid State Circuits, 32 (7): 968-976 (1997)22.1 A 90GS/s 8b 667mW 64× interleaved SAR ADC in 32nm digital SOI CMOS., , , , , , , , , and . ISSCC, page 378-379. IEEE, (2014)A 25Gb/s CDR in 90nm CMOS for High-Density Interconnects., , , , , and . ISSCC, page 1266-1275. IEEE, (2006)