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Disambiguation of "Gowda, Sudhir M."

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Integrated transversal equalizers in high-speed fiber-optic systems.

, , , , , , and . IEEE J. Solid State Circuits, 38 (12): 2131-2137 (2003)

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Sudhir Singh

Sudhir Bhiwapurkar

Sudhir Kumar

Sudhir Bhiwapurkar

Sudhir Bhiwapurkar

 

Other publications of authors with the same name

Custom design of CMOS low-power high-performance digital signal-processing macro for hard-disk-drive applications., , , , , and . IBM J. Res. Dev., 39 (1-2): 83-92 (1995)BSIM plus: an advanced SPICE model for submicron MOS VLSI circuits., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 13 (9): 1166-1170 (1994)Integrated transversal equalizers in high-speed fiber-optic systems., , , , , , and . IEEE J. Solid State Circuits, 38 (12): 2131-2137 (2003)Digital FIR filters for high speed PRML disk read channels., , , , , , , and . IEEE J. Solid State Circuits, 30 (12): 1517-1523 (December 1995)A 10Gb/s 5-Tap-DFE/4-Tap-FFE Transceiver in 90nm CMOS., , , , , , , , , and 5 other author(s). ISSCC, page 213-222. IEEE, (2006)A 10-Gb/s CMOS clock and data recovery circuit using a secondary delay-locked loop., , , , , , , and . CICC, page 81-84. IEEE, (2003)Testing of Analog Neural Array-Processor Chips., , and . ICCD, page 118-121. IEEE Computer Society, (1991)10+ Gb/s 90nm CMOS serial link demo in CBGA package., , , , , , , and . CICC, page 27-30. IEEE, (2004)10+ gb/s 90-nm CMOS serial link demo in CBGA package., , , , , , , and . IEEE J. Solid State Circuits, 40 (9): 1987-1991 (2005)Testing of programmable analog neural network chips., , and . VLSI Signal Processing, 8 (3): 267-282 (1994)