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Associative Memory based on clustered Neural Networks: Improved model and architecture for Oriented Edge Detection.

, , , , , and . DASIP, page 51-58. IEEE, (2016)

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An Introduction to High-Level Synthesis., , , and . IEEE Des. Test Comput., 26 (4): 8-17 (2009)Bitwidth-aware high-level synthesis for designing low-power DSP applications., , , and . ICECS, page 531-534. IEEE, (2010)Embedding polynomial time memory mapping and routing algorithms on-chip to design configurable decoder architectures., , , and . ICASSP, page 5036-5040. IEEE, (2014)A Dedicated Approach to Explore Design Space for Hardware Architecture of Turbo Decoders., , , , , , and . SiPS, page 288-293. IEEE, (2012)A design approach to automatically generate on-chip monitors during high-level synthesis of hardware accelerator., , and . ACM Great Lakes Symposium on VLSI, page 273-278. ACM, (2014)Virtual component IP re-use in telecommunication systems design: a case study of MPEG-2/JPEG2000 encoder., , and . ICECS, page 733-736. IEEE, (2002)Behavioral description model BDM for design space exploration: A case study of HIS algorithm for MC-CDMA system., , , and . EUSIPCO, page 1625-1629. IEEE, (2007)A design methodology for IP integration., , and . ISCAS (4), page 711-714. IEEE, (2002)Clone-Based Encoded Neural Networks to Design Efficient Associative Memories., , and . IEEE Trans. Neural Networks Learn. Syst., 30 (10): 3186-3199 (2019)Exploration and Generation of Efficient FPGA-based Deep Neural Network Accelerators., , , and . SiPS, page 123-128. IEEE, (2021)