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Disambiguation of "Ikeda, Mitsuo"

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An MPEG-2 Video Encoder LSI with Scalability for HDTV based on Three-layer Cooperative Architecture.

, , , , , , , and . DATE, page 44-. IEEE Computer Society / ACM, (1999)

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Yukihiro Ikeda

Mitsuyoshi Ikeda

Mitsuo Hori

Mitsuo Kitagawa

Shingo Ikeda

 

Other publications of authors with the same name

A Hardware/Software Concurrent Design for a Real-Time SP@ML MPEG2 Video-Encoder Chip Set., , , , , and . ED&TC, page 320-327. IEEE Computer Society, (1996)A 4: 2: 2P@ML MPEG-2 video encoder board using an enhanced MP@ML video encoder LSI., , , , and . IEEE Trans. Consumer Electronics, 45 (4): 1130-1133 (1999)H.265/HEVC encoder for UHDTV.. ASP-DAC, page 687-688. IEEE, (2015)Single-Chip MPEG-2 422P@HL CODEC LSI with Multi-Chip Configuration for Large Scale Processing beyond HDTV Level., , , , , , , , , and 1 other author(s). DATE, page 20002-20007. IEEE Computer Society, (2003)Global Rate Control Scheme for MPEG-2 HDTV Parallel Encoding System., , , and . ITCC, page 195-200. IEEE Computer Society, (2000)A distributed TS-MUX architecture for multi-chip extension beyond the HDTV level., , , , and . ISCAS (2), page 261-264. IEEE, (2004)Professional H.265/HEVC encoder LSI toward high-quality 4K/8K broadcast infrastructure., , , , , , , , , and 3 other author(s). Hot Chips Symposium, page 1-24. IEEE, (2015)MVC real-time video encoder for full-HDTV 3D video., , , , , , , , , and 2 other author(s). ICCE, page 166-167. IEEE, (2012)An HEVC real-time encoding system with high quality HDR color representations., , , , , , and . ICCE, page 1-2. IEEE, (2018)Multi-reference and multi-block-size motion estimation with flexible mode selection for professional 4: 2: 2 H.264/AVC encoder LSI., , , , and . ISCAS, page 800-803. IEEE, (2008)