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Accelerating recurrent neural networks in analytics servers: Comparison of FPGA, CPU, GPU, and ASIC.

E. Nurvitadhi, J. Sim, D. Sheffield, A. Mishra, K. Srivatsan, and D. Marr. FPL, page 1-4. IEEE, (2016)

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Debbie Beaudry

Diethard Marr

Ludwig Marr

Jürgen Marr

Stefanie Marr

Other publications of authors with the same name

WRPN: Wide Reduced-Precision Networks.A. Mishra, E. Nurvitadhi, J. Cook, and D. Marr. CoRR, (2017)In-Package Domain-Specific ASICs for Intel® Stratix® 10 FPGAs: A Case Study of Accelerating Deep Learning Using TensorTile ASIC.E. Nurvitadhi, J. Cook, A. Mishra, D. Marr, K. Nealis, P. Colangelo, A. Ling, D. Capalija, U. Aydonat, A. Dasu and 1 other author(s). FPL, page 106-110. IEEE Computer Society, (2018)High performance binary neural networks on the Xeon+FPGA™ platform.D. Moss, E. Nurvitadhi, J. Sim, A. Mishra, D. Marr, S. Subhaschandra, and P. Leong. FPL, page 1-4. IEEE, (2017)Apprentice: Using Knowledge Distillation Techniques To Improve Low-Precision Network Accuracy.A. Mishra, and D. Marr. ICLR (Poster), OpenReview.net, (2018)Customizable FPGA OpenCL matrix multiply design template for deep neural networks.J. Yinger, E. Nurvitadhi, D. Capalija, A. Ling, D. Marr, K. Srivatsan, D. Moss, and S. Subhaschandra. FPT, page 259-262. IEEE, (2017)Evaluating and Enhancing Intel® Stratix® 10 FPGAs for Persistent Real-Time AI.E. Nurvitadhi, D. Kwon, A. Jafari, A. Boutros, J. Sim, P. Tomson, H. Sumbul, G. Chen, P. Knag, R. Kumar and 6 other author(s). FPGA, page 119. ACM, (2019)A sparse matrix vector multiply accelerator for support vector machine.E. Nurvitadhi, A. Mishra, and D. Marr. CASES, page 109-116. IEEE, (2015)Why Compete When You Can Work Together: FPGA-ASIC Integration for Persistent RNNs.E. Nurvitadhi, D. Kwon, A. Jafari, A. Boutros, J. Sim, P. Tomson, H. Sumbul, G. Chen, P. Knag, R. Kumar and 6 other author(s). FCCM, page 199-207. IEEE, (2019)In-Package Domain-Specific ASICs for Intel® Stratix® 10 FPGAs: A Case Study of Accelerating Deep Learning Using TensorTile ASIC(Abstract Only).E. Nurvitadhi, J. Cook, A. Mishra, D. Marr, K. Nealis, P. Colangelo, A. Ling, D. Capalija, U. Aydonat, S. Shumarayev and 1 other author(s). FPGA, page 287. ACM, (2018)WRPN: Training and Inference using Wide Reduced-Precision Networks.A. Mishra, J. Cook, E. Nurvitadhi, and D. Marr. CoRR, (2017)

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Disambiguation of "Marr, Debbie"

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Accelerating recurrent neural networks in analytics servers: Comparison of FPGA, CPU, GPU, and ASIC.

Please choose a person to relate this publication to

Debbie Beaudry

Diethard Marr

Ludwig Marr

Jürgen Marr

Stefanie Marr

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Marr, Debbie"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Accelerating recurrent neural networks in analytics servers: Comparison of FPGA, CPU, GPU, and ASIC.

Please choose a person to relate this publication to

Debbie Beaudry

Diethard Marr

Ludwig Marr

Jürgen Marr

Stefanie Marr

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
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Accelerating recurrent neural networks in analytics servers: Comparison of FPGA, CPU, GPU, and ASIC.