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Ultra-wide voltage range designs in fully-depleted silicon-on-insulator FETs.

E. Beigné, A. Valentian, B. Giraud, O. Thomas, T. Benoist, Y. Thonnart, S. Bernard, G. Moritz, O. Billoint, Y. Maneglia, P. Flatresse, J. Noel, F. Abouzeid, B. Pelloux-Prayer, A. Grover, S. Clerc, P. Roche, J. Coz, S. Engels, and R. Wilson. DATE, page 613-618. EDA Consortium San Jose, CA, USA / ACM DL, (2013)

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Sylvain Broyer

Sylvain Mogliacci

Sylvain Marlière

Sylvain Jay

Sylvain Didelot

Other publications of authors with the same name

Statistical Characterization of Library Timing Performance.V. Migairou, R. Wilson, S. Engels, N. Azémard, and P. Maurine. PATMOS, volume 4148 of Lecture Notes in Computer Science, page 468-476. Springer, (2006)A Digital Event-Based Strategy for ASK demodulation.A. Jadue, S. Engels, and L. Fesquet. VLSI-SoC, page 244-245. IEEE, (2019)Ultra-wide body-bias range LDPC decoder in 28nm UTBB FDSOI technology.P. Flatresse, B. Giraud, J. Noel, B. Pelloux-Prayer, F. Giner, D. Arora, F. Arnaud, N. Planes, J. Coz, O. Thomas and 4 other author(s). ISSCC, page 424-425. IEEE, (2013)Product On-Chip Process Compensation for Low Power and Yield Enhancement.N. Moubdi, P. Maurine, R. Wilson, N. Azémard, V. Dumettier, A. Bansal, S. Barasinski, A. Tournier, G. Durieu, D. Meyer and 3 other author(s). PATMOS, volume 5953 of Lecture Notes in Computer Science, page 247-255. Springer, (2009)Bottom-up digital system-level reliability modeling.N. Amador, V. Huard, E. Pion, F. Cacho, D. Croain, V. Robert, S. Engels, P. Flatresse, and L. Anghel. CICC, page 1-4. IEEE, (2011)An Event-Based Strategy for ASK demodulation.A. Jadue, S. Engels, and L. Fesquet. EBCCSP, page 1-5. IEEE, (2019)A Novel Event-Based Method for ASK Demodulation.A. Jadue, S. Engels, and L. Fesquet. LASCAS, page 1-4. IEEE, (2022)Clockless Design Performance Monitoring for Nanometer Technologies.M. Renaudin, A. Buhrig, C. Guillemet, R. Wilson, and S. Engels. ASYNC, page 108-109. IEEE Computer Society, (2014)A Fine-Grain Variation-Aware Dynamic Vdd-Hopping AVFS Architecture on a 32 nm GALS MPSoC.I. Panades, E. Beigné, Y. Thonnart, L. Alacoque, P. Vivet, S. Lesecq, D. Puschini, A. Molnos, F. Thabet, B. Tain and 4 other author(s). IEEE J. Solid State Circuits, 49 (7): 1475-1486 (2014)On-Chip Process Variability Monitoring Flow.N. Moubdi, P. Maurine, R. Wilson, S. Engels, N. Azémard, V. Dumettier, and P. Busson. J. Low Power Electron., 6 (4): 601-606 (2010)

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Disambiguation of "Engels, Sylvain"

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Ultra-wide voltage range designs in fully-depleted silicon-on-insulator FETs.

Please choose a person to relate this publication to

Sylvain Broyer

Sylvain Mogliacci

Sylvain Marlière

Sylvain Jay

Sylvain Didelot

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Engels, Sylvain"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Ultra-wide voltage range designs in fully-depleted silicon-on-insulator FETs.

Please choose a person to relate this publication to

Sylvain Broyer

Sylvain Mogliacci

Sylvain Marlière

Sylvain Jay

Sylvain Didelot

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
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Ultra-wide voltage range designs in fully-depleted silicon-on-insulator FETs.