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A 120-MHz BW, 122-dBFS SFDR CTΔΣ ADC With a Multi-Path Multi-Frequency Chopping Scheme.

, , , , , , , and . IEEE J. Solid State Circuits, 59 (4): 1184-1193 (April 2024)

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15.2 A 2.2GHz continuous-time ΔΣ ADC with -102dBc THD and 25MHz BW., , , , , , , , , and . ISSCC, page 272-273. IEEE, (2016)A 3.2mW SAR-assisted CTΔ∑ ADC with 77.5dB SNDR and 40MHz BW in 28nm CMOS., , , , , , and . VLSI Circuits, page 230-. IEEE, (2019)A 2.2 GHz Continuous-Time ΔΣ ADC With -102 dBc THD and 25 MHz Bandwidth., , , , , , , , , and . IEEE J. Solid State Circuits, 51 (12): 2906-2916 (2016)A 28nm 6GHz 2b Continuous-Time ΔΣ ADC with -101 dBc THD and 120MHz Bandwidth Using Digital DAC Error Correction., , , , , , and . ISSCC, page 416-418. IEEE, (2022)A 2 GHz 0.98 mW 4-bit SAR-Based Quantizer with ELD Compensation in an UWB CT ΣΔ Modulator., , , , , , , , and . ISCAS, page 1-5. IEEE, (2018)A BiCMOS Operational Amplifier Achieving 0.33μV°C Offset Drift using Room-Temperature Trimming., , , , and . ISSCC, page 76-77. IEEE, (2008)A 4GHz CT ΔΣ ADC with 70dB DR and -74dBFS THD in 125MHz BW., , , and . ISSCC, page 470-472. IEEE, (2011)A 158-mW 360-MHz BW 68-dB DR Continuous-Time 1-1-1 Filtering MASH ADC in 40-nm CMOS., , , , , and . IEEE J. Solid State Circuits, 57 (12): 3781-3793 (2022)A 6GHz Multi-Path Multi-Frequency Chopping CTΔΣ Modulator achieving 122dBFS SFDR from 150kHz to 120MHz BW., , , , , , , and . VLSI Technology and Circuits, page 1-2. IEEE, (2023)Novel Baseband Analog Beamforming through Resistive DACs and Sigma Delta Modulators., , , , , , , and . ECCTD, page 1-4. IEEE, (2020)