( en | de | ru )

 

Disambiguation of "Jeong, Deog-Kyoon"

Author of the publication

copydeleteadd this publication to your clipboard
A 20 Gb/s 0.4 pJ/b energy-efficient transmitter driver architecture utilizing constant Gm.

, , , , , , , , and . A-SSCC, page 1-4. IEEE, (2015)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Su-Jeong Jeong

Wonrae Jeong

Hyung-Gon Jeong

Hang-Kyun Jeong

Chang-Kyo Jeong

 

Other publications of authors with the same name

A theoretical analysis of phase shift in pulse injection-locked oscillators., , , , , and . ISCAS, page 1662-1665. IEEE, (2016)A 10-Gb/s, 0.03-mm2, 1.28-pJ/bit Half-Rate All-Digital Injection-Locked Clock and Data Recovery with Maximum Timing-Margin Tracking Loop., , , , and . A-SSCC, page 73-76. IEEE, (2018)A 27.1 mW, 7.5-to-11.1 Gb/s single-loop referenceless CDR with direct Up/dn control., , and . CICC, page 1-4. IEEE, (2017)A 10-Gb/s 6-Vpp differential modulator driver in 65-nm CMOS., , and . ISCAS, page 1869-1872. IEEE, (2014)A Practical Implementation of IEEE 1588-2008 Transparent Clock for Distributed Measurement and Control Systems., and . IEEE Trans. Instrumentation and Measurement, 59 (2): 433-439 (2010)A 0.032mm2 3.1mW synthesized pixel clock generator with 30psrms integrated jitter and 10-to-630MHz DCO tuning range., , , , , and . ISSCC, page 250-251. IEEE, (2013)Practical considerations in the design and implementation of time synchronization systems using IEEE 1588., and . IEEE Communications Magazine, 47 (11): 164-170 (2009)A 10 Gb/s voltage swing level controlled output driver in 65-nm CMOS technology., and . ISOCC, page 53-56. IEEE, (2012)Virtual minimum potential queuing., , and . J. High Speed Networks, 16 (4): 323-339 (2007)A 10-Gb/s, 0.03-mm2, 1.28-pJ/bit Half-Rate Injection-Locked CDR With Path Mismatch Tracking Loop in a 28-nm CMOS Technology., , , , , and . IEEE J. Solid State Circuits, 54 (10): 2812-2822 (2019)