( en | de | ru )

 

Disambiguation of "Kuroda, Tadahiro"

Author of the publication

copydeleteadd this publication to your clipboard
A 5-GHz 0.15-mm2 Collision Avoidable RFID Employing Complementary Pass-transistor Adiabatic Logic with an Inductively Connected External Antenna.

, , , , , , and . A-SSCC, page 1-3. IEEE, (2021)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Tadahiro Ninomiya

Toshio Kuroda

Susumu Kuroda

Michelle Kuroda

 

Other publications of authors with the same name

Wearable sensor-based human activity recognition from environmental background sounds., and . J. Ambient Intell. Humaniz. Comput., 5 (1): 77-89 (2014)A 10-Bit 80-MS/s Decision-Select Successive Approximation TDC in 65-nm CMOS., , and . IEEE J. Solid State Circuits, 47 (5): 1232-1241 (2012)A 0.5 V 1.1 MS/sec 6.3 fJ/Conversion-Step SAR-ADC With Tri-Level Comparator in 40 nm CMOS., , , and . IEEE J. Solid State Circuits, 47 (4): 1022-1030 (2012)A 0.55 V 10 fJ/bit Inductive-Coupling Data Link and 0.7 V 135 fJ/Cycle Clock Link With Dual-Coil Transmission Scheme., , , , , , , and . IEEE J. Solid State Circuits, 46 (4): 965-973 (2011)An Inductive-Coupling DC Voltage Transceiver for Highly Parallel Wafer-Level Testing., , , , , , , and . IEEE J. Solid State Circuits, 45 (10): 2057-2065 (2010)A 20-Gb/s Simultaneous Bidirectional Transceiver Using a Resistor-Transconductor Hybrid in 0.11-µm CMOS., , , , , and . IEEE J. Solid State Circuits, 42 (3): 627-636 (2007)A 7-nm FinFET 1.2-TB/s/mm2 3D-Stacked SRAM Module With 0.7-pJ/b Inductive Coupling Interface Using Over-SRAM Coil and Manchester-Encoded Synchronous Transceiver., , , , and . IEEE J. Solid State Circuits, 58 (7): 2075-2086 (2023)A 0.5-V 5.2-fJ/Conversion-Step Full Asynchronous SAR ADC With Leakage Power Reduction Down to 650 pW by Boosted Self-Power Gating in 40-nm CMOS., , , , and . IEEE J. Solid State Circuits, 48 (11): 2628-2636 (2013)A 40-Gb/s CMOS clocked comparator with bandwidth modulation technique., , , , , , , , and . IEEE J. Solid State Circuits, 40 (8): 1680-1687 (2005)Low-power CMOS digital design with dual embedded adaptive power supplies., and . IEEE J. Solid State Circuits, 35 (4): 652-655 (2000)