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Disambiguation of "Clerc, Sylvain"

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27.1 A 460MHz at 397mV, 2.6GHz at 1.3V, 32b VLIW DSP, embedding FMAX tracking.

, , , , , , , , , , , , , , , , , , , , , and . ISSCC, page 452-453. IEEE, (2014)

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Christian Clerc

Hans-Georg Clerc

Gabriele Clerc

André Clerc

Hans Clerck

 

Other publications of authors with the same name

Comparative evaluation of Body Biasing and Voltage Scaling for Low-Power Design on 28nm UTBB FD-SOI Technology., , and . ISLPED, page 1-6. IEEE, (2019)On-chip supply power measurement and waveform reconstruction in a 28nm FD-SOI processor SoC., , , , , , , , and . A-SSCC, page 125-128. IEEE, (2016)40nm CMOS 0.35V-Optimized Standard Cell Libraries for Ultra-Low Power Applications., , , , , and . ACM Trans. Design Autom. Electr. Syst., 16 (3): 35:1-35:17 (2011)Ultra-wide voltage range designs in fully-depleted silicon-on-insulator FETs., , , , , , , , , and 10 other author(s). DATE, page 613-618. EDA Consortium San Jose, CA, USA / ACM DL, (2013)28nm CMOS, energy efficient and variability tolerant, 350mV-to-1.0V, 10MHz/700MHz, 252bits frame error-decoder., , , , and . ESSCIRC, page 153-156. IEEE, (2012)A 3.0μW@5fps QQVGA Self-Controlled Wake-Up Imager with On-Chip Motion Detection, Auto-Exposure and Object Recognition., , , , , , , , , and 1 other author(s). VLSI Circuits, page 1-2. IEEE, (2020)A 45nm CMOS 0.35v-optimized standard cell library for ultra-low power applications., , , , and . ISLPED, page 225-230. ACM, (2009)Scalable 0.35 V to 1.2 V SRAM Bitcell Design From 65 nm CMOS to 28 nm FDSOI., , , , , , , , and . IEEE J. Solid State Circuits, 49 (7): 1499-1505 (2014)27.1 A 460MHz at 397mV, 2.6GHz at 1.3V, 32b VLIW DSP, embedding FMAX tracking., , , , , , , , , and 12 other author(s). ISSCC, page 452-453. IEEE, (2014)A 0.32V, 55fJ per bit access energy, CMOS 65nm bit-interleaved SRAM with radiation Soft Error tolerance., , , , , and . ICICDT, page 1-4. IEEE, (2012)