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Disambiguation of "Clerc, Sylvain"

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A 0.32V, 55fJ per bit access energy, CMOS 65nm bit-interleaved SRAM with radiation Soft Error tolerance.

, , , , , and . ICICDT, page 1-4. IEEE, (2012)

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Christian Clerc

Hans-Georg Clerc

Gabriele Clerc

André Clerc

Hans Clerck

 

Other publications of authors with the same name

28nm FD-SOI technology and design platform for sub-10pJ/cycle and SER-immune 32bits processors., , , , , , , , and . ESSCIRC, page 108-111. IEEE, (2015)30% static power improvement on ARM Cortex®-A53 using static biasing-anticipation., , , , , , , and . ESSCIRC, page 37-40. IEEE, (2016)A 291nW Real-Time Event-Driven Spectrogram Extraction unit in 28nm FD-SOI CMOS for Keyword Spotting Application., , , , and . ESSCIRC, page 341-344. IEEE, (2023)A 0.40pJ/cycle 981 μm2 voltage scalable digital frequency generator for SoC clocking., , , , , and . A-SSCC, page 69-72. IEEE, (2017)Scalable 0.35 V to 1.2 V SRAM Bitcell Design From 65 nm CMOS to 28 nm FDSOI., , , , , , , , and . IEEE J. Solid State Circuits, 49 (7): 1499-1505 (2014)A 0.32V, 55fJ per bit access energy, CMOS 65nm bit-interleaved SRAM with radiation Soft Error tolerance., , , , , and . ICICDT, page 1-4. IEEE, (2012)27.1 A 460MHz at 397mV, 2.6GHz at 1.3V, 32b VLIW DSP, embedding FMAX tracking., , , , , , , , , and 12 other author(s). ISSCC, page 452-453. IEEE, (2014)On-chip supply power measurement and waveform reconstruction in a 28nm FD-SOI processor SoC., , , , , , , , and . A-SSCC, page 125-128. IEEE, (2016)Comparative evaluation of Body Biasing and Voltage Scaling for Low-Power Design on 28nm UTBB FD-SOI Technology., , and . ISLPED, page 1-6. IEEE, (2019)A 3.0μW@5fps QQVGA Self-Controlled Wake-Up Imager with On-Chip Motion Detection, Auto-Exposure and Object Recognition., , , , , , , , , and 1 other author(s). VLSI Circuits, page 1-2. IEEE, (2020)